AR# 64092

Aurora Design Assistant - Hardware Debug

描述

The Aurora Design Assistant walks you through the recommended design flow for Aurora 8B10B/ Aurora 64B66B designs while debugging commonly encountered issues, such as simulation issues, Initialization failures, and data errors.

The Design Assistant provides useful design and troubleshooting information, but also points you to the exact documentation you need to read to help you design efficiently with Aurora 8B10B/Aurora 64B66B.

Note: This Answer Record is a part of the Xilinx Aurora Solution Center (Xilinx Answer 21263).

The Xilinx Aurora Solution Center is available to address all questions related to Aurora 8B10B/Aurora 64B66B.

Whether you are starting a new design with Aurora or troubleshooting a problem, use the Aurora Solution Center to guide you to the right information.

解决方案

  • REFCLK should meet the phase noise requirements for the specific transceiver used.
    Refer to (Xilinx Answer 57738) for guidance related to debugging Reference Clock, Termination or Signal Integrity Problems.

  • Please note that CC logic/hot - plug circuits must always be enabled.
    From the Vivado 2015.1 release on, both Aurora cores have CC logic included inside the IP.

  • Refer to XAPP1192 - Aurora 64B66B (or) XAPP1193 - Aurora 8B10B to understand the steps to target an Aurora core to an evaluation board.
    Similar guidance applies to custom boards.

  • Ensure the Serial link is error free by using IBERT.
    If the Serial link is found to be faulty, debug the link issue.
    Refer to (Xilinx Answer 57237)

  • Appendix C, the Debug section in PG074 - Aurora 64B66B (or) PG046 - Aurora 8B10B provides the steps to debug various design issues.

  • For 7 series devices, Aurora cores use DFE as the default equalizer.
    Please refer to "Choosing Between LPM and DFE Modes" in the GTX/GTH transceiver user guide and switch the equalizer to LPM if required.
    For 7 series GTP transceivers, only the LPM option is available.

  • For Virtex-6 GTX, if the clocks with link partners are synchronous, please refer to (Xilinx Answer 57538) for CDR setting update.

  • Refer to the Top Issues section of the Aurora Solution Center (Xilinx Answer 21263) and fix any existing known issues.

  • You should always check the GT attributes in the core with respect to GT wizard output, as it will have the latest attribute settings for better GT performance.
    For UltraScale cores, GT wizard is called as a sub-core by the Aurora cores, so the attributes are expected to be up to date
    .

 

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
61912 Aurora Solution Center - Design Assistant N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
57538 Aurora 8B10B - Virtex-6 - CDR settings for synchronous operation N/A N/A
57237 Xilinx HSSIO Solution Center - Design Assistant Serial Transceiver Debugging N/A N/A
AR# 64092
日期 07/01/2015
状态 Active
Type 解决方案中心
IP