AR# 64097

2014.4 Vivado Simulator - Post Synthesis simulation fails to compile due to package file called in the testbench not compiled


When running "Post Synthesis Functional Simulation", I receive the following errors which did not occur in "Behavioral Simulation". 

INFO: [VRFC 10-307] analyzing entity packed_samples_wrap
INFO: [VRFC 10-163] Analyzing VHDL file "C:/testcase/Vivado/packed_samples.srcs/sim_1/imports/vhdl/packed_samples_wrap_TB.vhd" into library xil_defaultlib
ERROR: [VRFC 10-149] 'packed_samples_pkg' is not compiled in library xil_defaultlib [C:/testcase/Vivado/packed_samples.srcs/sim_1/imports/vhdl/packed_samples_wrap_TB.vhd:26]

According to the error the "packed_samples_wrap_pkg.vhd" file is not getting compiled.

Is this a known issue and how can I work around it?


This is a known issue when using package files in VHDL and trying to use the settings within your testbench for "Post Synthesis Functionl/Timing Simulation".

The package file is not being included in the project file (.prj) generated for simulation compilation.

It is only included for implementation in the GUI even though they are added as both simulation and implementation sources.

To work around the issue:

  1. Avoid using constants etc defined in the package file in your testbenches when simulating "Post Synthesis" or "Post Implementation" design.
  2. The other option is to generate the simulation scripts only by selecting the "Generate Scripts Only" option in the Simulation Settings.
    Then go to <project_dir>/<project_name>.sim/simset/synth(impl)/func(timing)/ and edit the PRJ file to include the package file for compilation.
    After saving the modified PRJ file, manually run "compile.bat", "elaborate.bat" and "simulate.bat" from the command prompt to launch simulation.

This issue no longer occurs in Vivado 2015.1.



Answer Number 问答标题 问题版本 已解决问题的版本
58878 Xilinx Simulation Solution Center - Design Assistant - Vivado Simulator - Functional Simulation N/A N/A
AR# 64097
日期 04/15/2015
状态 Active
Type 综合文章