UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64440

UltraScale FPGA GTY Transceiver - Known Issues and Answer Record List

描述

This answer record lists the known issues and answer records associated with the Virtex UltraScale FPGA GTY Transceiver.

解决方案

Usage:


(Xilinx Answer 66647)UltraScale GTH and GTY transceivers bias voltage on MGTAVTT caused by negative current under some startup conditions 
(Xilinx Answer 66160)ADS - Example simulation project using IBIS-AMI models of UltraScale GTY 
(Xilinx Answer 66341)UltraScale GTY Transceiver: TX and RX Latency Values
(Xilinx Answer 66517)Manual Eye Scan with UltraScale GTY in 10 steps
(Xilinx Answer 66341)UltraScale GTY Transceiver: TX and RX latency values
(Xilinx Answer 65111)UltraScale RX/TXUSRCLK routing
(Xilinx Answer 59834)My UltraScale device package is showing 2 power groups for the MGT power supplies when there is only one column of GTs
(Xilinx Answer 64062)UltraScale GTY RX reset in Near End PMA loopback (TX->RX serial loopback)
(Xilinx Answer 62527)UltraScale GTY: how to set the CDR to "lock to local reference clock"
(Xilinx Answer 64103)UltraScale GTH/GTY TX/RX PROG DIV block reset requirements
(Xilinx Answer 61723)UltraScale GTH and GTY transceivers reference clock AC coupling capacitor value
(Xilinx Answer 63391)My UltraScale GTY line rate violates the minimum value in Table 58 of the data sheet
(Xilinx Answer 63704)UltraScale GTH/GTY - How to switch to use internal PRBS pattern generator when using Asynchronous Gearbox mode
(Xilinx Answer 64012)Synchronous gearbox normal (non-CAUI) usage for 128-bit fabric interface (64-bit internal) UltraScale GTY
(Xilinx Answer 61946)Virtex UltraScale GTY - UG578 v1.0 - incorrect description for reference clock selection above 16.375 Gbps
(Xilinx Answer 62261)Datarate limitation for GTY TX Phase Interpolator usage

Wizard:

(Xilinx Answer 57487)UltraScale FPGA Transceiver Wizard - Release Notes and Known Issues for Vivado 2013.4 and newer versions
(Xilinx Answer 65228)How to share a COMMON block using GTH transceivers
(Xilinx Answer 58437)Vivado - UltraScale Transceivers Wizard [Route 35-54] unrouted nets
(Xilinx Answer 62977)UltraScale GTH/GTY SATA COMINIT/COMAWAKE burst numbers are higher by 1
(Xilinx Answer 62548)My GTY/GTH refclk output is not toggling
(Xilinx Answer 62730)2014.3 - IBERT - UltraScale - RESETFSM_OVERRIDE bit is set to 1 by default

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54480 LogiCORE IP JESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
AR# 64440
日期 09/03/2019
状态 Active
Type 已知问题
器件
的页面