AR# 64615

描述

Version Found: DDR4 v7.1, DDR3 v7.1

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

The product guide recommends ROW_COLUMN_BANK for the ordering of the memory controller.

Due to changes in the MIG controller for UltraScale, this will cause low performance for AXI interfaces.

解决方案

To improve the efficiency of the AXI interface, the parameter AUTO_AP_COL_A3 should be set to "ON" in the RTL located in the files below.

You will need to update the file which matches the memory type you have selected:

• DDR3- mig_v7_1_ddr3_mem_intfc.sv
• DDR4 - mig_v7_1_ddr4_mem_intfc.sv

Revision History:

06/25/2015 - Initial Release

链接问答记录

主要问答记录