AR# 64615


UltraScale DDR4/DDR3 - AXI Interface efficiency improvements for 2015.2


Version Found: DDR4 v7.1, DDR3 v7.1

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

The product guide recommends ROW_COLUMN_BANK for the ordering of the memory controller.

Due to changes in the MIG controller for UltraScale, this will cause low performance for AXI interfaces.


To improve the efficiency of the AXI interface, the parameter AUTO_AP_COL_A3 should be set to "ON" in the RTL located in the files below.

You will need to update the file which matches the memory type you have selected:

  • DDR3-
  • DDR4 -

Revision History:

06/25/2015 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 64615
日期 01/02/2018
状态 Active
Type 已知问题
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