UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 65111

UltraScale RX/TXUSRCLK routing

描述

In UltraScale devices can I cross SLR boundaries with TX/RXUSRCLKs?

Can I use an MCMM to drive USRCLKs?

解决方案

When the TX/RXUSRCLK ports are driven by separate outputs (for example when the USRCLK and the USRCLK2 are different frequencies), then the skew between the inputs becomes critical.

In this situation only the routing options shown in the User Guide are allowed, TX/RXOUTCLK to BUFG_GT to TX/RXUSRCLK.


With the option of the TX/RXPROGDIVCLK and the divider options in the BUFG_GT there should be never be a need to use an MMCM to create USERCLKs.

The skew between separate outputs of an MMCM will normally be too much.

When the same BUFG is driving the USRCLK and USRCLK2 port the skew should always be minimal.

In addition, the skew between separate paths crossing an SLR boundary will normally be too much.


In Vivado 2015.3 the timing between the USRCLK inputs will be strictly enforced by the software.

If the USRCLK/2 are both at the same frequency you can drive an MMCM with the ODIV2 output of the IBUFDS_GTE to create the USRCLKS as long as the link is synchronous.

If the link is not synchronous you cannot create the clock that way unless the link uses clock correction.  See the clock correction section in the User Guide.

AR# 65111
日期 11/27/2019
状态 Active
Type 综合文章
器件
的页面