AR# 65219

UltraScale RLDRAM3 - older versions of MIG UltraScale RLDRAM IP cause critical warnings in 2015.3


Version Found: RLDRAM v1.0

Version Resolved: See (Xilinx Answer 69037)

A new DRC check has been added in Vivado 2015.3 on usage of the FIFO36E2 primitive.

It will cause critical warnings if an older MIG UltraScale RLDRAM3 IP is brought into Vivado 2015.3 without upgrading to the latest IP version.

The following CRITICAL WARNING might be seen:

CRITICAL WARNING: [DRC AVAL-247] Independent_clock_check: The FIFO36E2 cell u_af has CLOCK_DOMAINS=INDEPENDENT. However the two clock pins, RDCLK and WRCLK, are driven by the same driver. The expected property value for CLOCK_DOMAINS for this clocking connectivity is COMMON. Improperly setting this attribute can impact simulation, optimization, and timing for the FIFO resulting in incorrect simulation behavior, potential loss of performance, and increase in power.


To resolve the critical warning, upgrade the IP to RLDRAM3 v1.0 in Vivado 2015.3.

If you are unable to upgrade the IP, please contact Xilinx Technical Support through the Xilinx Service Portal:

Revision History:

08/14/2015Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
69037 UltraScale/UltraScale+ RLDRAM3 - Release Notes and Known Issues N/A N/A
AR# 65219
日期 12/19/2017
状态 Active
Type 已知问题