AR# 65676


Zynq UltraScale+ MPSoC, SDIO - SDIO Receiver Auto Tuning Fails In SD104/eMMC 200 Modes


Programming the delay taps inside an SDIO controller delay-locked loop (DLL) non-sequentially might lead to failing of auto-tuning.


The issue can be resolved by changing the SD clock frequency. The work-around sequence is as follows:

After receiving the "tuning done" or before issuing a new tuning request from the SDIO controller
  1. Gate the SD clocks using the clock control register
  2. Program the SDCLK Frequency Select of the clock control register with a value different from the previously programmed value (For example if the current value is 200 MHz, program a value of 100 MHz).
  3. Wait for the Internal Clock Stable bit of the clock control register
  4. Program the desired frequency (For example 200MHz).
  5. Un-gate the SD clocks
  6. Proceed to the normal SD transactions

This behavior will be documented in a future version of (UG1085) Zynq UltraScale+ Technical Reference Manual, currently planned for v1.6.

AR# 65676
日期 04/21/2017
状态 Active
Type 综合文章
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