AR# 65906

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Aurora 8B10B v11.0 - 4-byte core fails in simulation during elaboration stage

描述

Simulation of an Aurora 8B10B example fails during the elaboration stage with the following error:

Error (suppressible): ./../../../aura_aurora_8b10b_rev11p0_example.srcs/sources_1/ip/aura_aurora_8b10b_rev11p0/aura_aurora_8b10b_rev11p0/gt/aura_aurora_8b10b_rev11p0_gt.vhd(1019): (vopt-1130) Port "STABLE_CLOCK" of entity "aura_aurora_8b10b_rev11p0_gtrxreset_seq" is not in the component being instantiated.

解决方案

This issue applies to an Aurora 8B10B 4-byte core targeting 7 series GTH/GTP.

Update the following in the <component_name>_gtrxreset_seq.v[hd] file.

Step1:

Delete the STABLE_CLK port and make a wire initialized to 1'b0 as shown below.

Wire STABLE_CLK = 1'b0;

Step2:

Update the value of the c_flop_input parameter for the "rst_cdc_sync" and "gtrxreset_in_cdc_sync" synchronizers to 1'b0:

c_flop_input    => 0

This issue is fixed in the 2015.4 release of Vivado Design Suite.

Revision History:

11/05/2015 - Initial Release

02/24/2016 - Updated to mention about target GT's

AR# 65906
日期 03/04/2016
状态 Active
Type 综合文章
器件
Tools
IP
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