AR# 66193

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Zynq UltraScale+ MPSoC - What are the limitations of the PS DDR controller? Which device should I choose?

描述

The PS DDR in Zynq UltraScale+ is able to support most JEDEC configurations.

What are the limitations?

解决方案

Table 17-1 of UG1085 Zynq UltraScale+ Technical Reference Guide lists the limitations of the DRAM and topologies that are supported.

Also see (DS925) Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics for maximum speeds, and (UG583) UltraScale Architecture PCB Design for PCB requirements.

Additional limitations for LPDDR4:

  • 6 Gb, 12 Gb, 24 Gb, and 32 Gb (per die) densities are not supported.
  • Byte-Mode devices are not supported.

These will be added to v1.6 of (UG1085).

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
66194 Zynq UltraScale+ MPSoC - Processing System (PS) DDR Controller N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
66194 Zynq UltraScale+ MPSoC - Processing System (PS) DDR Controller N/A N/A
AR# 66193
日期 07/07/2017
状态 Active
Type 综合文章
器件
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