UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 67203

Vivado_Implementation: How to understand and Debug I/O and clock placer errors

描述

This Answer Record includes techniques that can be used to understand and fix I/O and clock placer errors.

解决方案

To understand the root cause of the I/O clock placer failure, it is necessary to understand what components are failing to get placed and what rules apply to those components so that it is possible to identify the rule that is the root cause of the failure.

The I/O and clock placer error messaging in Vivado is verbose and very helpful in understanding the reason for the error. 

The first section of the error message states what the problem is and whether the problem would lead to sub-optimal routing or whether the connection is entirely unroutable. It then lists the names of the components involved in the failure. 

The next section of the error message lists the rules which are related to components involved. The STATUS value of each rule states whether the design met the rule or not.

By examining the problem with the placement, and cross referencing it with all of the other rules being applied to the failed components, it is possible to understand why no feasible was available. 


For example an error might occur where a BUFR was not placed in the same clock region as a RAMB load component which is an invalid and unroutable placement. 

The rules involved are that the BUFR must be in the same clock region as its I/O clock input, and it must also be in the same clock region as its loads. 

But consider a case where a RAMB is driven by two BUFRs, each sourced from different clock regions. It is not possible to place both BUFRs and the RAMB in the same clock region, so a faulty placement occurs and it is flagged as an error.

The following are some additional techniques that can be used to gather more information when debugging I/O and clock placement failures:



1) Using the place_ports command to view partially placed design:


When place_design fails, it does not leave a partial placement available in memory to examine. It is possible to run the place_ports command instead so as to reproduce the same error while providing the resulting partial placement for examination.

This command runs I/O and clock placement and leaves this partial placement in memory for investigation. 

Open the synthesized design and run the following commands:

opt_design
place_ports

You can then examine the placement of I/O port, GT, clock buffer, MMCM and PLL instances in the device view. 

This will help you to understand why the tool is not able to use the correct site for the failing cell as you can examine the expected site location for conflicts (for example, because the site is pre-occupied by some other cell or if the cell is part of another shape which is forcing the tool to place the cell at its expected site)



2) Using the CLOCK_DEDICATED_ROUTE constraint:

Many clock placement errors fall into a category of errors where the error can be overridden by setting the constraint CLOCK_DEDICATED_ROUTE= FALSE. 

The error message provides the constraint syntax necessary to accomplish the override. Typically the errors occur because a clock signal would be routed sub-optimally or not at all due to the faulty placement.

It can be useful to override the error so that the placer continues and the faulty placement can be examined. This override should not be used to generate a bitstream unless the suboptimal routing is understood and deemed acceptable.

For more details on this constraint and use cases refer to page 173 of (UG949):

https://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf



3) Using the report_clock_utilization command to export clock placer floor plan:


The I/O and clock placer create a complicated floorplan for the global and regional clocks in the design so that clock regions are not over-utilized. This includes pblock constraints that assign each clock domain with a list of clock regions it can use.

The report_clock_utilization command using the -write_xdc switch can be used to export the clock placer's floor plan for examination and even editing.

This command also reports the clock primitive utilization, clock root assignments, routing resource utilization per clock regions, clocks net names and their loads in each clock region.


This command should be run after running the place_ports (see above) command so that the floorplan has already been generated. 

In cases where the placer over-subscribed clock region with too many clocks, this report can be used to identify the clocks which are being assigned to the problematic clock region. 

Later you can modify the pblock constraints to move the clock which have non-fixed loads to a different clock region which have free global clock resources.

This report can also be used to identify the clocks for which too few clock regions have been assigned which might have resulted in a fitting failure.

In this case you can modify the pblock constraints to assign a higher number of clock regions to the loads of the problematic clock.

For more details on how to modify the clock placer floorplan, refer to (Xilinx Answer 66386).


AR# 67203
日期 04/06/2017
状态 Active
Type 综合文章
器件
Tools
的页面