AR# 67230

UltraScale DDR4 - tREFI interval is incorrectly set


Version Found: DDR4 v2.0

Version Resolved: See (Xilinx Answer 69035)

There is a bug in the tREFI counter logic. It should checking if it has reached one, not zero.

If an IP is generated with a tREFI of 7.8us in simulation it is actually set to 7.805us which will cause a 9xtREFI violation.


To work around the problem, the tREFIF parameter inside needs to be updated to the following:

localparam tREFIF = tREFIFR*RANKS - 1; //fix tREFI interval

To modify the IP RTL files, you can manually edit with a text editor. However, if the output products are regenerated, the modifications will be overwritten by Vivado.

As an alternative, you can create a custom IP Repository using the following steps:

1) Copy the DDR4 Controller directory from your Vivado install area.

For example:

(Full IP) C:\Xilinx\Vivado\2016.1\data\ip\xilinx\mem_v1_2

2) Make your edits to the source code in this copied directory and store the files in a location of your choice. Somewhere in your project directory is recommended.

(Full IP) make the following edits to line 179:

localparam tREFIF = tREFIFR*RANKS - 1; //fix tREFI interval

3) You will then need to add it in the IP Catalog. Click on the IP Settings:


4) Then Add a Repository, point to the newly edited PHY directory, and Refresh All.

The IPs in the repository should be displayed in the lower box.


The following screen capture is an example of what it should look like:


The IP in the standard MIG directory will now be over-written and you will see your edits when you generate the IP and look at the relevant code.

Revision History:

05/16/2016 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 67230
日期 01/17/2018
状态 Active
Type 已知问题
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