When using the CNTVALUEIN port on the I/ODELAY, a maximum adjustment of 8 taps only is permitted.
How can a change of more than 8 taps be achieved?
Note: this Answer Record should not be viewed in isolation.
For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)
When making large delay changes using the CNTVALUEIN port, it is possible that the delay can become unstable and cause the delay to shift in to an unknown region.
This issue applies to the Native and Component mode use of either the IDELAY or ODELAY independent of the DELAY_FORMAT.
In Native mode if a delay of more than 8 taps is needed, then the clock to the Bitslice should be disabled.
This can be done using the TBYTE_IN with TX_GATING enabled (by using the High Speed SelectIO Wizard).
Using this approach, the following sequence should be followed when doing a delay change of more than 8 taps:
There is a caveat to the above:
TX_GATING does not apply to BITSLICE_0 and BITSLICE_6 (where available) of each nibble and therefore, the TYBYTE_IN will have no effect.
As a result, this work-around cannot be used for these pins and the maximum adjustment must be restricted to 8 taps.
If multiple changes to the delay line are required then there is also a wait requirement.
As listed above, when EN_VTC of the Bitslice is de-asserted you need to wait a minimum of 10 clock cycles, any subsequent accesses (either INC/DEC or LOAD) to the delay line requires a 5 clock cycle wait.
For example, for multiple LOADs: