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  1. Xilinx -灵活应变.万物智能.
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  3. AR# 67412: Zynq UltraScale+ MPSoC: 2016.2 FSBL, Added DDR ECC Initialization feature

AR# 67412

Zynq UltraScale+ MPSoC: 2016.2 FSBL, Added DDR ECC Initialization feature

描述

In order to add ECC support to the DDR, the FSBL needs to handle the following:

  • Specific DDR Configuration
  • Initializing the DDR to a known value

解决方案

In Vivado 2016.2, FSBL now supports DDR ECC Initialization.
AR# 67412
日期 06/22/2016
状态 Active
Type 综合文章
器件
  • Zynq UltraScale+ MPSoC
Tools
  • Vivado Design Suite - 2016.2
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