描述

When you generate the FIFO Generator core with asynchronous reset configuration, there is a chance that empty (or *valid in the case of AXI interface) signals will be deasserted without a valid write operation.

This can happen if the asynchronous reset is deasserted exactly at the rising edge of the clock(s) and the Enable Safety Circuit option is used.

This behavior might also be observed with the AXI Interface of a FIFO generator core.

This issue is seen in post synthesis simulations and in hardware.

解决方案

The screen capture below is from post synthesis simulation of an AXI Stream FIFO which demonstrates this issue.

• s_aresetn is asserted low for three rising clock edges and is getting deasserted exactly at the rising edge of m_aclk
• s_axis_tvalid stays low throughout this wave segment, though there is a write operation (s_axis_tvalid is low)
• m_axis_tvalid is low before reset (so the FIFO is empty) but it goes high after reset even when no data is written in to the FIFO.

This is a known issue in Vivado 2016.1 and 2016.2. The issue is seen in designs which have "safety circuit" enabled. (The Safety circuit is always enabled when using the AXI interface).

To fix this issue, you must either install the patch for Vivado 2016.2 or ensure that the reset deassertion does not happen exactly at the rising edge of the clock(s).

Please follow the instructions in the readme file to install the patch. The user logic which is interacting with the FIFO IP must also be modified as mentioned in the ReadMe file. 

The attached Timing_relation.jpg shows when the outputs from FIFO are valid.

This issue has been fixed in the Vivado 2016.3 release.

附件