Version Found: All versions prior to MIG 7 Series v4.0 rev1
Version Resolved: See (Xilinx Answer 54025)
Xilinx has identified a case where the required periodic reads are not issued during continuous write commands.
MIG 4.1 to be released with Vivado 2016.3 will have a fix for this controller issue. This answer record includes information regarding the update and whether the updates are recommended within new and existing DDR3 systems.
Details on this issue:
The issue exists with the MIG 7 Series DDR3 memory controller.
Note: PHY Only designs are not affected.
The issue occurs when a refresh command (issued by either a user command or by Trefi time intervals) and a periodic read create a collision within the 7 Series DDR3 memory controller.
When this collision occurs, the periodic reads stop while the memory controller continues to issue write commands. As soon as the next read transaction is issued by the user interface, the periodic reads resume.
So the missing periodic reads recover automatically once a read command is issued by the user interface.
Periodic reads are a part of the continuous calibration that is exercised during normal operation. Periodic reads are used for VT variation tracking on the read bus.
This possible pause of periodic read is not likely to affect customer systems for the following reasons:
Because of this, the update is not required in existing memory systems. For new designs, it is recommended to use the latest version of Vivado and MIG.
09/21/2016 - Initial Release