Version Found: v1.1 Rev1 (Vivado 2016.2)
Version Resolved and other Known Issues: (Xilinx Answer 65751)
When generating the UltraScale+ PCI Express Integrated Block core for xcvu9p-flgc2104 and xcvu9p-flga2577 with non-default GT locations, the tools gives the following error message when opening the example design:
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
This is a known issue and will be fixed in a future release of the core. For Vivado 2016.2, please install the tactical patch attached as described below:
Note: The "Version Found" column lists the version the problem was first discovered. The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions. This is an issues with latency of the core.
08/16/2016 - Initial Release