Initial Lane Alignment is the second stage in JESD204 link up, following Code Group Synchronization.
This step synchronizes the lanes and ensures the lanes are properly aligned. Once they are aligned, user data transmission can begin.
Initial Lane Alignment is achieved by means of an initial lane alignment sequence, starting immediately after Code Group Synchronization.
An initial lane alignment sequence transmitted by an ADC consists of exactly 4 multiframes.
An initial lane alignment sequence required by Subclass 1 and 2 DACs consists of exactly 4 multiframes also.
Link setups with multiple Subclass 0 DACs might require additional multiframes to achieve lane alignment.
Details on the make-up of each multiframe is available in the JESD204 Specification, available from the JEDEC website: https://www.jedec.org/sites/default/files/docs/JESD204B.pdf
In the Xilinx JESD204B core, RX register Debug Status bit 2 goes high when this stage begins (Start of ILA is detected) and Debug Status bit 3 goes high when this stage completes and data transmission begins (Start of Data is detected).
Debugging Initial Lane Synchronization Issues:
Check link parameters are matching at both ends of the link. Different vendors can have values offset by 1 (For example for F = 4, 0x03 should be used. A DAC / ADC vendor might use 0x04 on their register / parameter).
It is important that the link parameters match at both the JESD204 core end and at the DAC / ADC.
Lanes are not aligned. Check layout and run IBERT.
Noise on lanes causes data integrity issues. Check layout and run IBERT as it will most likely show a high number of errors.