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AR# 67957

UltraScale/UltraScale+ Memory IP - "Phy core regeneration & stitching failed" occurs when opening an older Vivado project without upgrading the Memory IP

描述

Version Found: DDR4/3 v2.1; RLD3 v1.3, QDRII+ v1.3; QDRIV v1.2

Version Resolved: See (Xilinx Answer 58435)

When opening a Vivado project in 2016.3 that was created with an older Vivado version, implementation will fail with the following error if the Memory IP is not upgraded:

[Mig 66-119] Phy core regeneration & stitching failed. Please check vivado.log and debug_core_synth.log files in the directory

解决方案

The PHY IP is required to be updated in each Vivado release. If the full IP cannot be upgraded, please open a Service Request.

Release History:

10/05/2016 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 67957
日期 01/02/2018
状态 Active
Type 已知问题
器件
  • Kintex UltraScale
  • Kintex UltraScale+
  • Virtex UltraScale
  • More
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
Tools
  • Vivado Design Suite - 2016.3
IP
  • MIG UltraScale
的页面