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AR# 68177

UltraScale+ GTH Transceiver: TX and RX Latency Values

描述

This answer record provides the TX and RX latency values for the GTH transceiver in the Kintex/Virtex UltraScale+ FPGA and Zynq UltraScale+ MPSoC device families. 

解决方案

 

 

Please scroll down for tables:

 

 

 

 

 

TX:

 

 

Internal Data Width 16 20 32 40 Comments
Min Max Min Max Min Max Min Max  
TX Fabric Interface Fabric width Fabric width Fabric width Fabric width Double the * values if TX_FABINT_USRCLK_FLOP = 1b1 (Default is 0). Parenthesized numbers apply when Asynchronous Gearbox (Gearbox FIFO) is used.
16 32 20 40 32 64 40 80
16* 48 20* 60 32* 96 40* 120
(33*) (99)
PCIe 128B/130B Encoder         96 - 126       0 if bypass
8B/10B encoder     20 20     40 40 0 if bypass
Synchronous Gearbox
(Legacy Gearbox)
32-64 32-64     64-128 64-128     64B66B 0 if bypass. Applies also to CAUI mode.
32-66 32-66     64-130 64-130     64B67B 0 if bypass. Parenthesized range is for CAUI mode.
(64-132) (64-132)
Asynchronous Gearbox
(Gearbox FIFO)
      309-340 309-340     64B66B only 0 latency when unused. When used, TX Phase FIFO is bypassed with 0 latency. If non-default TXGBOX_FIFO_INIT_RD_ADDR (IRA) is used, add (4IRA)*66 UI to latency. CAUI numbers are expected to be close to this range (309 340).
TX Phase FIFO
40-56
(56-72)
40-56
(56-72)
50-70
(70-90)
50-70
(70-90)
80-112
(112-144)
80-112
(112-144)
100-140
(140-180)
100-140
(140-180)
Using TX FIFO. Parenthesized value applies if TXFIFO_ADDR_CFG = HIGH. (Default LOW)
16 16 20 20 32 (0 when using Gearbox FIFO) 32 (0 when using Gearbox FIFO) 40 40 Bypassing TX FIFO.
To TX PCS/PMA boundary 16 16 20 20 32 32 40 40  
To Serializer 32 32 40 40 64 64 80 80 Using TX FIFO or Gearbox FIFO: 2 TXUSRCLK cycles (extra reg stage for improved setup margin).
8 8 10 10 16 16 20 20 Bypassing TX FIFO and Gearbox FIFO: 1/2 cycle into Serializer.
PMA 15 15 15 15 15 15 15 15 Serializer.
Total -- absolute minimum for a given internal data width 71 85 127 155 Fabric Interface (NxN) + TX FIFO bypass + To TX PCS/PMA boundary + To Serializer + PMA.
Total -- XAUI (8B/10B mode) with TX FIFO     165 225     315 435 Fabric Interface (min NxN, max 2NxN) + 8b10b + TX FIFO (latency variation after reset) + To TX PCS/PMA boundary + To Serializer + PMA.
Total PCIe Gen3 (128B/130B)         223-253       Fabric Interface (32x32) + 128B/130B Encoder + TX FIFO bypass + To TX PCS/PMA boundary + To Serializer + PMA.

 

Notes:

1) Using the TXGBOX_FIFO_LATENCY DRP Register:

Actual latency through TX Asynchronous Gearbox exceeds the latency reported by the TXGBOX_FIFO_LATENCY (DRP Attribute) by 65.5 UI. 

The latency reported by the attribute is in units of 1/8th UI. As a result, the value read out from the attribute has to be divided by 8 before adding the offset.

2) Using the Latency table for high line rates:

In addition to the TX and RX latencies in the tables above, you will need to take account of the following:

a) When TX and RX FIFO are bypassed.

User will have to add additional 1 UI latency for each 1 Gbps increment in line rate beyond 2 Gbps to the PMA latency. ( TX path:0.3 UI, RX path:0.7 UI, Total:1.0 UI )

b) When RX FIFO is enabled and TX FIFO is bypassed.

User will have to add additional 2 UI latency for each 1 Gbps increment in line rate beyond 2 Gbps to the PMA latency.

 

For example:

From the table, for a particular use case, if the total latency (TX data path + Rx data path) results in 400 UI and if the intended line rate of operation is 12 Gbps, the user will need to add 10 UI (1 UI * 10) when TX and RX FIFO are bypassed. 

As a result, the final latency is 400 UI + 10 UI = 410 UI.

 

 

RX:

 

Internal Data Width 16 20 32 40 Comments      
Min Max Min Max Min Max Min Max        
PMA 40.5 40.5 44.5 44.5 60.5 60.5 68.5 68.5
       
PMA to PCS 0 0 0 0 0 0 0 0 RX FIFO used      
8 8 10 10 16 16 20 20 RX FIFO bypass: 1/2 cycle latency.      
Internal Parallel Loopback: PCS TX to RX 16 16 20 20 32 32 40 40 For internal parallel loopback only and when RX FIFO is used. Latency from "To TX PCS/PMA boundary" of TX Table.      
Comma Alignment 32 55 40 69 64 103 80 129 Variability covers multiple modes. Parenthesized min is for XAUI. Bracketed max is for RXSLIDE PMA mode with PCS shifter.      
[33] (60) [41] [65] (120) [81]      
16 16 20 20 32 32 40 40 No Comma Alignment.      
8B/10B decoder     20 20     40 40 0 if bypass      
Elastic buffer
24+ 8xML
 
(ML = CLK_COR_
MIN_LAT)
40 + 8xML
 
(ML = CLK_COR_
MIN_LAT)
30 + 10xML
50 + 10xML
48 + 8xML
80+ 8xML
60 + 10xML
100 + 10xML
0 if bypass
 
 
See important note concerning CLK_COR_MIN_LAT following the table.
For 2 byte: 4 ML 6 (phase only)
11 ML 13 (clock correction)
**Use ML = 6 for calculation
For 4 byte : 8 ML 12 (phase only)
23 ML 27 (clock correction)
**Use ML = 12 for calculation
Note concerning CLK_COR_MIN_LAT: the value ranges shown for CLK_COR_MIN_LAT in the table are simplified guidelines for the purpose of showing sample latency ranges in the last 3 rows of the table. Use the CLK_COR_MIN_LAT value from the wizard as ML for actual latency calculations.
 
Phase Only is for FAST MODE
Asynchronous Gearbox
(Gearbox FIFO)
        252-348 252-348     64B66B only 0 latency when unused. If non-default RXGBOX_FIFO_INIT_RD_ADDR (IRA) is used, add (4IRA)*66 UI to latency. 4 is the default value for the attribute.      
Synchronous Gearbox
(Legacy Gearbox)
16-49    
32-97
(32-98)
    64B66B 0 if bypass. Parenthesized range is for CAUI mode.      
16-50    
32-98
(32-100)
    64B67B 0 if bypass. Parenthesized range is for CAUI mode.      
RX fabric interface Fabric width Fabric width Fabric width Fabric width        
16 32 20 40 32 64 40 80      
16* 48 20* 60 32* 96 40* 120 Fabric interface latency. Double the * values if RX_FABINT_USRCLK_INT = 1b1 (Default is 0). Parenthesized numbers apply when Gearbox FIFO is used.      
(33*) (99)      
  0, 16       0, 32-33     Extra latency when using gearboxes (0 or 1 RXUSRCLK cycle), due to possible need for extra pipelining to align frame within fabric word.      
PCIe Decoder and Block Alignment (128B/130B)         97-127       Decoder is synchronous, but its latency varies continuously within this range during normal operation.      
PCIe RX Elastic Buffer         See table below       The FIFO commonly alternates between two latencies 32 UI apart in normal operation. The remaining 64 UI of variation depends on startup conditions when the FIFO starts receiving valid data.      
Total -- absolute minimum for given internal data width 81 95 141 169 PMA (round up) + PMA to PCS (FIFO bypass) + Comma Alignment bypass + Fabric Interface (NxN)      
Total -- XAUI (highest latency mode)     235 304     449 578 PMA (round up) + PMA to PCS (zero-cycle setup) + Comma Alignment (XAUI mode) + 8B/10B + Elastic Buffer (latency variation after reset) + Fabric Interface (min NxN, max 2NxN)      
Total PCIe Gen3 (Common Clock mode)         416-509       PMA (round up) + PMA to PCS (zero-cycle setup) + RXSLIDE PMA mode (with Comma Alignment) + PCIe Gen3 Align/Decode + PCIe Elastic Buffer + Fabric Interface (32x32).      

 

Notes:

1) Using the RXGBOX_FIFO_LATENCY DRP Register.

Actual latency through the TX Asynchronous Gearbox exceeds the latency reported by the RXGBOX_FIFO_LATENCY (DRP Attribute) by 32 UI. 

The latency reported by the attribute is in units of 1/8th UI. So, the value read out from the attribute has to be divided by 8 before adding the offset.

2) Using the COMMA_ALIGN_LATENCY DRP Register.

To determine actual latency using the COMMA_ALIGN_LATENCY register, use the following procedure:

Latency = 2*Internal Data Width + DRP value from COMMA_ALIGN_LATENCY register

3) Using the Latency table for high line rates.

In addition to the TX and RX latencies in the tables above you will need to take account of the following:

a) When TX and RX FIFO are bypassed:.
 

User will have to add additional 1 UI latency for each 1 Gbps increment in line rate beyond 2 Gbps to the PMA latency. ( TX path:0.3 UI, RX path:0.7 UI, Total:1.0 UI )

b) When RX FIFO is enabled and TX FIFO is bypassed:

User will have to add additional 2 UI latency for each 1 Gbps increment in line rate beyond 2 Gbps to the PMA latency.

 

For example:

From the table, for a particular use case, if the total latency (TX data path + RX data path) results in 400 UI and If the intended line rate of operation is 12 Gbps, the user will need to add 10 UI (1 UI * 10) when TX and RX FIFO are bypassed. 

As a result, the final latency is 400 UI + 10 UI = 410 UI.

 

PCIe RX Elastic Buffer Latency:

 

PCIE3_CLK_COR_MIN_LAT PCIe Elastic Buffer Latency
Min Max
0 160 224
1 192 256
2 256 320
3 288 352
4 320 416
5 352 448
6 384 480
7 416 512
8 448 544
9 480 576
10 512 608
11 544 640
12 576 672
13 608 704
14 640 736
15 672 768

 

 

AR# 68177
日期 03/11/2019
状态 Active
Type 综合文章
器件
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