AR# 68266

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2016.4 Vivado Timing/Speed Files - UltraScale - How to address skew violation between RIU_CLK and PLL_CLK on a BITSLICE_CONTROL found when running new speed files

描述

(Xilinx Answer 68169) for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs details the new minimum production speed specification version (Speed File) required for all designs.

If you have run timing with the new speed files and have skew violations between the RIU_CLK and PLL_CLK, the next step is to use the script attached to this Answer Record to resolve the skew violations.

解决方案

Several solutions are available:

  • Recommended solution: migrate your project to Vivado 2016.4 and run the normal synthesis and implementation flow.
    The Vivado 2016.4 placer and router automatically constrain the BITSLICE_CONTROL clock routing in order to meet the BITSLICE_CONTROL clock skew requirements.
  • Second solution: continue using an older Vivado release for your project, including for running synthesis and implementation.
    Use the Tcl script (reportBSC.tcl) attached to this Answer Record to generate the BITSLICE_CONTROL clock routing constraints to be added to your next implementation run.
    See the instructions below for generating the constraints, or for fixing the skew violations with Vivado 2016.4 on an existing routed DCP.
    Use Vivado 2016.4 to run timing signoff (report_timing_summary) on the routed DCP and fix any remaining setup/hold violations (see (Xilinx Answer 68267)).
  • Third solution: continue using an older Vivado release with the corresponding speed files patch (limited to certain Vivado releases, available upon request), including for running synthesis and implementation.
    Use the Tcl script (reportBSC.tcl) attached to this Answer Record to generate the BITSLICE_CONTROL clock routing constraints to be added to your next implementation run.
    See the instructions below for generating the constraints, or for fixing the skew violations with an older release on an existing routed DCP.

Fixing BITSLICE_CONTROL skew violations on a routed DCP

1) Download the attached reportBSC.tcl script and save to the project working directory.

2) Open the routed Design Checkpoint (DCP).

3) Type the following in the Tcl console:

# Source Tcl procs
source reportBSC.tcl -notrace

set riuClkPins [reportBSC]
# reportBSC parses report_pulse_width and returns a list of BITSLICE_CONTROL/RIU_CLK pins with skew violations
set bscClkNets [constrainBSC $riuClkPins]
# generates bsc.xdc file and returns a list of nets that need re-implemented

4) Re-implement the violating clock nets by typing the following in the Tcl console:

route_design -unroute -nets [get_nets $bscClkNets]
read_xdc bsc.xdc
update_clock_routing
# Valid command for Vivado 2016.1 and newer. For older releases, use "place_design" instead
route_design -nets [get_nets $bscClkNets]

5) If you are using Vivado 2016.4, analyze the timing results with "report_pulse_width -max_skew" or "report_timing_summary (pulse width section)" to confirm all skew violations are fixed.

If you are using an older Vivado release, run "reportBSC" and review the log file. 

If setup or hold violations are found, see (Xilinx Answer 68267)

Generating BITSLICE_CONTROL clock routing constraints for Vivado releases (between 2015.3 and 2016.3)

1) Download the attached reportBSC.tcl script and save it to the project working directory.

2) Open the routed Design Checkpoint (DCP).

3) Type the following in the Tcl console:

# Source Tcl procs
source reportBSC.tcl -notrace
constrainBSC
# generates bsc.xdc file for MIG IPs that require the BITSLICE_CONTROL skew check

4) Add the bsc.xdc file to your design constraints for your next implementation runs.

5) If you are using Vivado 2016.4, analyze the timing results with "report_pulse_width -max_skew" or "report_timing_summary (pulse width section)" to confirm all skew violations are fixed.

If you are using an older Vivado release, run "reportBSC" and review the log file.


Revision History:

12/12/2016 Initial Release

附件

文件名 文件大小 File Type
reportBSC.tcl 12 KB TCL

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AR# 68266
日期 12/20/2016
状态 Active
Type 综合文章
器件
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