AR# 68794


LogiCORE IP SMPTE UHD-SDI v1.0 (Rev. 3) 2016.4 - UHD-SDI core shows Timing Errors on EDH TX paths


I am getting timing errors on the EHD TX paths for certain implementation runs of the UHD-SDI core v1.0 Rev 3 in Vivado 2016.4.

This happens in certain runs only, based on the logic routing paths chosen by the core.

There are already multicycle path constraints for all of the EDH paths (as show below), but the existing constraint do not seem to cover all of the paths.

Below are the Timing Constraints in the UHD-SDI core in the file v_smpte_uhdsdi_rxtx_core.xdc:

set EDHcells [get_cells -hier -regexp -filter {IS_PRIMITIVE && IS_SEQUENTIAL} .*EDH.*]

set_multicycle_path -setup -from $EDHcells 10
set_multicycle_path -hold -from $EDHcells 9

Below is one of the timing errors. 

The requirement listed is 3.3ns which is from the txoutclk. However the TX EDH does not need to be constrained with the 3.3ns clock and so can be assigned a multicycle path constraint, similar to the RX EDH path constraints.

Name Path 201
Slack -0.044ns
Source uhdsdi_demo/sdi_4ch_rxtx/genblk1[0].sdi_wrapper_support/sdi_wrapper/uhdsdirxtx/inst/TX/TXEDH/EDH_CRC/ff_crc_reg_reg[8]/C (rising edge-triggered cell FDRE clocked by txoutclk_out[0] {rise@0.000ns fall@1.667ns period=3.333ns})
Destination uhdsdi_demo/sdi_4ch_rxtx/genblk1[0].sdi_wrapper_support/sdi_wrapper/uhdsdirxtx/inst/TX/TXEDH/EDH_TX/checksum_reg[8]/D (rising edge-triggered cell FDRE clocked by txoutclk_out[0] {rise@0.000ns fall@1.667ns period=3.333ns})
Path Group txoutclk_out[0]
Path Type Setup (Max at Slow Process Corner)
Requirement 3.333ns (txoutclk_out[0] rise@3.333ns - txoutclk_out[0] rise@0.000ns)

Data Path Delay 3.225ns (logic 1.388ns (43.039%) route 1.837ns (56.961%))
Logic Levels 10 (CARRY8=2 LUT2=1 LUT5=3 LUT6=3 MUXF7=1)
Clock Path Skew -0.180ns
Clock Uncertainty 0.035ns
Clock Net Delay (Source) 2.761ns (routing 1.024ns, distribution 1.737ns)
Clock Net Delay (Destination) 2.404ns (routing 0.935ns, distribution 1.469ns)


This is an issue in the UHD-SDI core v1.0 Rev3 in Vivado 2016.4, where the existing constraints generated by the core do not seem to cover all of the TX EDH paths.

The patch for 2016.4 can be downloaded from (Xilinx Answer 68741). This issue is fixed in the 2017.1 release.



AR# 68794
日期 05/05/2017
状态 Active
Type 综合文章
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