Version Found: v2.2
Version Resolved: See (Xilinx Answer 69035)
The UltraScale DDR4 IP added support for MT40A1G16WBU-083E in version 2.2.
If the specified device is xcku115-flvb2104-2-e and the Data Width is set to 80 bits, the design will fail to generate output products with the following messaging:
To work around this issue, follow the steps below:
set_param memory.reset_in_non_address_bank true