Version Found: DDR4 v1.0, DDR3 v1.0, RLDRAM3 v1.0, QDRII+ v1.0, QDRIV v1.0, LPDDR3 v1.0
Version Resolved: See (Xilinx Answer 58435)
In Vivado 2015.3 and onwards, pblock constraints for UltraScale Memory IP will be generated by the Vivado Placer during place_design.
These pblock constraints created by the Vivado Placer are hidden and not visible to the user.
The Vivado Placer will also perform proper CLOCK_ROOT assignment and delay matching to meet the max_skew requirement between the RIU_CLK and PLL_CLK pins of the BITSLICE_CONTROL.
If you add your own pblock constraints for the UltraScale Memory IP, then:
In order to meet the max_skew requirement between the RIU_CLK and PLL_CLK pins of the BITSLICE_CONTROL, the following constraints must be applied to the clock networks for proper CLOCK_ROOT assignment and delay matching.