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AR# 68976

UltraScale/UltraScale+ Memory IP - User addition of pblock might cause skew violations between RIU_CLK and PLL_CLK pins of BITSLICE_CONTROL

描述

Version Found: DDR4 v1.0, DDR3 v1.0, RLDRAM3 v1.0, QDRII+ v1.0, QDRIV v1.0, LPDDR3 v1.0

Version Resolved: See (Xilinx Answer 58435)

In Vivado 2015.3 and onwards, pblock constraints for UltraScale Memory IP will be generated by the Vivado Placer during place_design.

These pblock constraints created by the Vivado Placer are hidden and not visible to the user.

The Vivado Placer will also perform proper CLOCK_ROOT assignment and delay matching to meet the max_skew requirement between the RIU_CLK and PLL_CLK pins of the BITSLICE_CONTROL.

If you add your own pblock constraints for the UltraScale Memory IP, then:

  • The user-defined pblock for UltraScale Memory IP will be used and the Vivado Placer will not generate the hidden pblock constraints.
  • The Vivado Placer will not perform proper CLOCK_ROOT assignment and delay matching to meet the max_skew, this could potentially lead to max_skew timing issues

解决方案

In order to meet the max_skew requirement between the RIU_CLK and PLL_CLK pins of the BITSLICE_CONTROL, the following constraints must be applied to the clock networks for proper CLOCK_ROOT assignment and delay matching.

# The X#Y# value for the USER_CLOCK_ROOT property should be the CLOCK_REGION where the MIG MMCM is located
set_property USER_CLOCK_ROOT X#Y# [get_nets -of [get_pins {myRIUClkBufG/O myPLLClkBufG/O}]]
set_property CLOCK_DELAY_GROUP migPblockCDG0 [get_nets -of [get_pins {myRIUClkBufG/O myPLLClkBufG/O}]]

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 68976
日期 01/12/2018
状态 Active
Type 已知问题
器件 More Less
Tools
IP
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