This Xilinx Answer describes the required step to program/boot from a board with QSPI wired in x1 (legacy MOSI-MISO) to a Zynq UltraScale+ MPSoC device.
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|Design Type||PS Only|
|SW Type||FSBL, u-boot|
|PS Features||QSPI in x1 mode (legacy MOSI-MISO)|
|Xilinx Tools Version||2017.1|
This article covers the main changes you will need to make in order to use the QSPI wired in x1.
Vivado Processing System IP
Below is a snapshot of the configuration used in Vivado to operate the QSPI in x1 (legacy MOSI-MISO).
Note DQ0 is MOSI, DQ1 is MISO.
The command used to load the various partitions needs to be a x1 READ command.
Depending on the boot mode (QSPI24 or QSPI32) the proper initialization function needs to be updated.
In XFsbl_Qspi24Init(), change to the following:
In XFsbl_Qspi32Init(), change to the following:
The DTS node related to QSPI needs to be modified to operate in QSPI single x1.
Below are the key attribute modifications:
After the BOOT.bin is created following the standard flow, it can be programmed to the QSPI by following the steps in (Xilinx Answer 68657) How to use u-boot to program a "known to work" QSPI flash?
Remembere to use the FSBL.elf and u-boot.elf specifically generated for the QSPI x1 configuration.
Boot from flash:
Select the appropriate boot mode (QSPI24 or QSPI32) and power up the board.
It is important to know that the CSU ROM will always try to boot in the most efficient way, trying to read the QSPI in x4 first.
If this is NOT successful than it will try x1.
Later in the flow, the FSBL generated above will load the partitions in QSPI x1.