AR# 69248


2017.1/2 Zynq UltraScale+ MPSoC: PetaLinux Device-tree generator does not set gtr_sel0 polarity correctly for dual lane DisplayPort design


In my design I configure the Display Port to dual lower.

I provide my own HDF, but the gtr_sel0 polarity is not set correctly by the device-tree generator, which results in the DisplayPort not coming up with Zynq UltraScale+ MPSoC evaluation boards.


In the 2017.1/2 release, the PetaLinux device-tree generator does not generate the right dual lane DisplayPort device-tree node.

To fix this issue follow the steps below:

1) Apply the attached patch to the device-tree recipe: <plnx-proj-root>/project-spec/meta-user/recipes-bsp/device-tree/device-tree-generation_%.bbappend

Note: To apply a patch to recipes, please refer to (UG1144) or

device-tree-generation_%.bbappend file content:

SRC_URI_append ="\
    file://0001-Fix-for-gtr_sel0-polarity-correct-for-dual-lane-DP.patch \

FILESEXTRAPATHS_prepend := "${THISDIR}/files:"


文件名 文件大小 File Type
0001-Fix-for-gtr_sel0-polarity-correct-for-dual-lane-DP.patch 929 Bytes PATCH
AR# 69248
日期 08/21/2017
状态 Active
Type 综合文章
Boards & Kits
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