2. 技术支持
  3. AR# 6925:
  4. AR# 69250: LogiCORE IP MIPI CSI-2 Transmitter Subsystem v1.0 (Rev. 2) - Why is the MIPI Transmitter Clock/Data relationship not center-aligned for some line-rate configurations?

AR# 69250

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LogiCORE IP MIPI CSI-2 Transmitter Subsystem v1.0 (Rev. 2) - Why is the MIPI Transmitter Clock/Data relationship not center-aligned for some line-rate configurations?

描述

The MIPI protocol requires clock/data to be in center-aligned relation.

When using a 7 Series device, and a MIPI CSI-2 Transmitter (TX) Subsystem generated from Vivado 2017.1, the MIPI Transmitter Clock/Data output relationship is not center-aligned for some line-rate configurations (for Example 600Mbps).

This issue could cause some MIPI receiver devices without the Clock/Data skew calibration feature to fail.

解决方案

This issue occurs in Vivado 2017.1 generated LogiCORE MIPI CSI-2 Transmitter IP. 

This issue will be fixed on Vivado 2017.2.

If you are using the 2017.1 version, you can download the LogiCORE IP MIPI CSI-2 Transmitter Subsystem v1.0 (Rev. 2) patch from (Xilinx Answer 69173) that will fix the MMCM phase setting issue and resolve the Clock/Data relationship.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69173 2017.1 LogiCORE IP MIPI CSI-2 Transmitter Subsystem v1.0 (Rev. 2) - Patch Updates for the LogiCORE IP MIPI CSI-2 Transmitter Subsystem v1.0 (Rev. 2) N/A N/A
54550 LogiCORE IP MIPI D-PHY - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions N/A N/A
AR# 69250
日期 06/06/2017
状态 Active
Type 综合文章
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