The MIPI protocol requires clock/data to be in center-aligned relation.
When using a 7 Series device, and a MIPI CSI-2 Transmitter (TX) Subsystem generated from Vivado 2017.1, the MIPI Transmitter Clock/Data output relationship is not center-aligned for some line-rate configurations (for Example 600Mbps).
This issue could cause some MIPI receiver devices without the Clock/Data skew calibration feature to fail.
This issue occurs in Vivado 2017.1 generated LogiCORE MIPI CSI-2 Transmitter IP.
This issue will be fixed on Vivado 2017.2.
If you are using the 2017.1 version, you can download the LogiCORE IP MIPI CSI-2 Transmitter Subsystem v1.0 (Rev. 2) patch from (Xilinx Answer 69173) that will fix the MMCM phase setting issue and resolve the Clock/Data relationship.