When the MIPI CSI-2 Receiver Subsystem for 7 Series is configured with the Clock/Data skew calibration set to Auto/Fixed, it will use an IDELAYCTRL resources in each clock region.
IP generated from Vivado 2016.4, 2017.1, or 2017.2 have IODELAY_GROUP set to a fixed "mipi_dphy_v3_0_1_dly_grp" setting.
If the user instantiates multiple IP in the same device, it will trigger an implementation error in Vivado.
This issue occurs in the LogiCORE MIPI CSI-2 Receiver Subsystem, generated from:
This issue will be fixed in Vivado 2017.3.
If you are using the Vivado 2017.2 version, you can download the LogiCORE IP MIPI CSI-2 Receiver Subsystem v2.1 (Rev. 1) patch from (Xilinx Answer 69431).
This will fix the IODELAY_GROUP setting for each of the IPs.
If you are using Vivado 2016.4 or Vivado 2017.1, you will need to upgrade your design to the 2017.2 version before applying the patch from (Xilinx Answer 69431).
As suggested by (PG202)/(PG232) Chapter 4 (Design Flow Steps),
The user needs to select the "Include IDELAYCTRL in core" option for one of their IP cores. For the rest of the IP cores, this option should be unselected.