AR# 69701

Zynq UltraScale+ RFSoC: RF Data Converter IP Change Log

描述

This is the complete list of Fixes and Enhancements for the RF Data Converter IP.

解决方案

2019.1: Version 2.1 (Rev. 2)

  • Bug Fix: Fixed the demonstration testbench data checker for DAC Nyquist zone 2
  • Bug Fix: Fixed the demonstration testbench data checkers for DAC and ADC inverted Q output
  • Bug Fix: Fixed issue where the GUI would allow reference clock frequencies above the maximum supported by the PLL
  • Bug Fix: Fixed rounding issue for the data stimulus block clock in the IP Integrator example design
  • New Feature: Added support for RF Analyzer
  • New Feature: Added background calibration bypass option
  • New Feature: Added an interrupt for when the POR Finite State Machine detects an error in the power-up sequence
  • Other: Added parameter for total number of slices per Tile
  • Other: Changed Mixer Type to "Off" for ADC slices 1 and 3 when in Bypass IQ->IQ mode
  • Other: Removed the "_i" extension from the component name in the IP Integrator example design
  • Other: Removed the following parameters which were not used by the IP DAC_AdderXY_Enable, DAC_FifoXY_Enable, DAC1_Output_Current and DAC2_Output_Current,  ADC_FifoXY_Enable
  • Other: Removed ADC/DAC debug options from IP GUI
  • Other: Removed calibration time option from GUI
  • Other: Removed pblock constraints from example design
  • Other: Reduced maximum ADC sample rate for gen 2 devices

 

2018.3.1: Version 2.1 (Rev. 1)

  • Bug Fix: Fixed GUI issue where switching between Simple and Advanced Setup without making any change would sometimes cause the GUI to not update correctly
  • Bug Fix: Fixed issue where the example design data capture block failed to capture the requested number of samples
  • Bug Fix: Set the FREQ_HZ parameter on clk_adcX and clk_dacX to an integer
  • Bug Fix: Fixed issue where frequency in DAC slice 3 was incorrect when updating using NCO Real-Time ports
  • Feature Enhancement: Increased Max ADC sampling rate for 5G support


2018.3: Version 2.1

  • Port Change: Added new debug port for powerup state monitoring
  • Bug Fix: Fixed DAC minimum sampling rate from 100MHz to 500MHz
  • Bug Fix: Fixed issue where Multi Tile Sync could be enabled when interpolation/decimation values did not match
  • Bug Fix: Fixed issue where Multi Tile Sync could be enabled when slice 0 in a Tile was not enabled
  • Bug Fix: Fixed ADC scaling output factor for Real to Complex configurations
  • Bug Fix: Fixed issue where an early state machine restart for one tile could interfere with the operation of another
  • Bug Fix: Fixed issue where post-implementation simulations could fail when ADC0 or DAC0 were disabled
  • Bug Fix: Fixed issue where reads from the HSCOM_PWR register could get incorrect data
  • New Feature: Added support for Multiband
  • New Feature: Added support for Real Time NCO changes via dedicated ports
  • New Feature: Added counters for unexpected resets in each tile. Values stored in register Tile BaseAddress + 0x38
  • New Feature: Added option to modify reference clock divider
  • Feature Enhancement: Changed default value of Mixer Type to "Off" from "Bypass"
  • Other: Added PLL Summary Tab to GUI
  • Other: IP GUI widgets have been updated
  • Other: Interpolation/Decimation parameter values have been changed (x4->4 and x8->8)
  • Other: Increased the AXI-4Lite timeout by a factor of 4
  • Other: Added memory based data stimulus and capture blocks to example design
  • Other: Modified demo testbench data generation and checking. Data is now analyzed in the frequency domain

 

2018.2: Version 2.0 (Rev. 1)

  • Bug Fix: Fixed DAC PLL Vco range for sampling rates above 6.4GSPS
  • Bug Fix: Set max ADC sampling rate to 4.096GHz for ZU25/27/28DR devices
  • Bug Fix: Fix issue with Multi Tile SYNC sysref counters. Previous counters could fail to meet the minimum threshold value
  • Bug Fix: Fixed issue with the opening of the example design in Windows
  • Bug Fix: Updated PLL VREG setting
  • Feature Enhancement: Improved AXI to DRP access times
  • Feature Enhancement: Disabled interpolation filter on unused paths
  • Feature Enhancement: Removed LUTAR methodology warning
  • Feature Enhancement: Implemented new PLL lock procedure
  • Feature Enhancement: Wait for de-assertion of AXI-Streaming reset before completing start-up
  • Other: Changed example design name to rfdc_ex to reduce path lengths
  • Other: Increased minimum PLL reference clock from 50MHz to 102.4062MHZ


2018.1: Version 2.0

  • Port Change: Removed user_sysref port and replaced with optional dac_user_sysref and adc_user_sysref ports. See product guide for more information.
  • Port Change: Added ADC over voltage and over range to the real time signal ports
  • Port Change: Re-named ADC real time signal and calibration freeze ports
  • Port Change: Changed Calibration Freeze Port interface to per tile. No change to actual ports
  • Port Change: Removed bit 15 from ADC and DAC cmn_control debug ports
  • Bug Fix: Fixed issue with ADC CONTROL_COMMON inputs being tied all to same input
  • Bug Fix: Fixed synthesis issue when ADC calibration mode is set to mode1, data output is I/Q and mixer is bypassed
  • Bug Fix: Fixed issue with ADC/DAC tile debug ports (pll_dmon, pll_lock, status and done) not being driven
  • Bug Fix: Always enable the DAC Vdda bleeder
  • New Feature: Added support for Multi Tile SYNC
  • New Feature: Added GUI option to enable/disable dither
  • New Feature: Added GUI option to speed-up Calibration Time
  • New Feature: Added GUI option for Auto Calibration Freeze
  • New Feature: Added GUI option for Simple Converter Set-up
  • New Feature: Added support for creating example design in IP Integrator
  • Feature Enhancement: Updated ADC calibration freeze settings
  • Feature Enhancement: Enhanced Vco settings
  • Feature Enhancement: Freeze calibration when over-voltage or over-range converter outputs are asserted
  • Feature Enhancement: Cleared datapath, fabric and decoder interrupts after start-up
  • Feature Enhancement: Reset the ADC NCO phase to align I and Q output on 4GSPS ADCs
  • Feature Enhancement: Increased Max Sampling Rates for ADC and DAC.
  • Feature Enhancement: Optimized calibration process to shorten start up time
  • Feature Enhancement: Added support for NCO frequencies above Fs/2
  • Feature Enhancement: Improved GUI layout
  • Other: Removed GUI option to select external/internal SYSREF
  • Other: Release AXI IPIF files into same directory as the other HDL

2017.4: Version 1.1

  • No changes

2017.3: Version 1.1

  • Bug Fix: 2017.3_uspea_updates
  • Bug Fix: Negative Quadrature option is only available when Fine Mixer is enabled
  • Bug Fix: Tile and Slice interrupts are now enabled by default
  • Bug Fix: Link Coupling is now an option for each individual ADC Tile
  • Bug Fix: Corrected coarse mixer settings
  • Bug Fix: Fixed reset of state machines when supplies or clocks are lost
  • Bug Fix: Fixed issue regarding tile resets and restarts. Please see product guide for detailed information
  • Bug Fix: AXI Streaming bus widths depend on the number of AXI4-lite words per clock cycle
  • Bug Fix: Fixed issue where in some configurations Clock Out Frequency was not listing all valid frequencies
  • Bug Fix: Removed invalid samples per AXI4-Stream word values from GUI when IQ data selected
  • Bug Fix: Fixed issue that could cause in some occasions incorrect data to be returned from a read to a DRP register
  • Bug Fix: Corrected DAC decoder output order
  • Bug Fix: Corrected ADC calibration constants and sequence
  • Bug Fix: 2017.3_updates
  • Bug Fix: Fixed DAC interpolation data register setting for IQ data
  • Bug Fix: Fixed issue where SYSREF Source was enabled only when DAC Tile 228 PLL was enabled
  • Bug Fix: Maximum ADC output clock frequency has been reduced to avoid min-pulse-width violations
  • Bug Fix: Corrected 2GSPS ADC IQ to IQ data routing
  • Bug Fix: NCO values now updated on a per tile basis rather then per individual slice
  • Bug Fix: Fine mixer settings fixed for negative quadrature option
  • Bug Fix: Fixed negative NCO frequency setting in ADC calibration mode 1
  • Bug Fix: Increased time for regulators to settle
  • Bug Fix: Ensured clock divider is set correctly after a reset
  • Bug Fix: Fixed the setting of the fine mixer NCO frequency on windows
  • Feature Enhancement: 2017.3_uspea_updates
  • Feature Enhancement: Added option to GUI for selecting Nyquist Zone
  • Feature Enhancement: Added option to GUI for selecting DAC Decoder Mode
  • Feature Enhancement: Added option to GUI to select the Coarse mixer frequency
  • Feature Enhancement: Added option to GUI for debug ports
  • Feature Enhancement: Added option to GUI to save and load custom presets
  • Feature Enhancement: Added support for Fine NCO mixer
  • Feature Enhancement: Added a register to set the power up sequence timer
  • Feature Enhancement: Added a new input user_sysref. See product guide for more information
  • Feature Enhancement: Updated PLL and ADC calibration settings
  • Feature Enhancement: Added location constraints of converters
  • Feature Enhancement: Added option to GUI to disable analog clock detection
  • Feature Enhancement: Added option to GUI to select DAC output current
  • Feature Enhancement: Added option to GUI to select ADC calibration mode
  • Feature Enhancement: 2017.3_updates
  • Feature Enhancement: Improved PLL lock performance
  • Feature Enhancement: Added Over Range and Over Voltage interrupts to ADC
  • Feature Enhancement: BUFG GTs have been added on all DAC and ADC output clocks
  • Feature Enhancement: Added support in ADC for IQ->IQ when Mixer is bypassed
  • Feature Enhancement: Added support for real time control of the converters
  • Feature Enhancement: Added register to disable the converter FIFOs
  • Feature Enhancement: Disabled unused Mixer and FIFO when in IQ->IQ mode to reduce power consumption
  • Feature Enhancement: Added calibration freeze when the ADC input is lost
  • Other: 2017.3_uspea_updates
  • Other: Reduced behavioral simulation start up time
  • Other: Restricted write access to some of the DRP registers
  • Other: Power down PLL in tiles where it is not being used
  • Other: Added delay between power-up state machine so converters do not all start at the same time
  • Other: 2017.3_updates
  • Other: Bypassed PLL fractional divider
  • Other: Optimized post-implementation speed up registers
  • Other: Removed medium and low BW decimation and interpolation options

2017.2: Version 1.0

  • No changes

2017.1: Version 1.0

  • General: Initial Release
AR# 69701
日期 07/01/2019
状态 Active
Type 综合文章
器件
Tools