UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 69827

UltraScale+ Memory IP - The SFVB784 package has incorrect data rates in PL Memory Interfaces

描述

Version Found: DDR4 v2.2 (Rev. 1), DDR3 v1.4 (Rev. 1), RLDRAM3 v1.4 (Rev. 1), QDRII+ v1.4 (Rev. 1), QDRIV v2.0 (Rev. 1), LPDDR3 v1.0 (Rev. 1)

Version Resolved: See (Xilinx Answer 58435)

(DS922) v1.5 August 29th, 2017 Table 27, shows valid data rates for various packages in PL Memory Interfaces.

The SFVB784 package is limited to one speed grade lower than All FFV packages when run above 1600 Mb/s.

In Vivado 2017.2 and earlier releases, if the user selects a SVFB784 package and customizes a PL Memory Interface, the data rates are incorrect in the Customization GUI for the selected memory device.

The data rates are the same as All FFV packages.

解决方案

In Vivado 2017.3, the issue has been corrected in the Customization GUI to reflect (DS922) v1.5 August 29th, 2017 Table 27.

The SFVB784 package is now limited to one speed grade lower than All FFV packages when run above 1600 Mb/s.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 69827
日期 12/20/2017
状态 Active
Type 综合文章
器件
Tools
IP
的页面