UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 69966

LDPC Encoder/Decoder v1.0 - Decoder produces incorrect DOUT data and parity flag for single block in a corner case.

描述

In the regression test of LDPC Encoder/Decoder, a single block is incorrectly decoded in one of the tests.

The failure is limited to one block of incorrect data output.

解决方案

This is a known issue in LDPC Encoder/Decoder v1.0 of Vivado 2017.3, which has been fixed in the 2017.4 release.

A particular sequence of events (block scheduling, early termination) has hit a condition of the scheduler that results in an LDPC code layer length being read incorrectly for one layer of the block.

This results in the particular block output being incorrect (along with the associated parity check). The circuit recovers and subsequent blocks are decoded correctly.

This behavior has only been seen in one test, after several months of randomized testing, so it is a low probability event.

For other LDPC Encoder/Decoder known issues, please refer to (Xilinx Answer 69399)

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69399 LDPC Encoder/Decoder - Vivado 2017.3 及更新工具版本的发布说明和已知问题 N/A N/A
AR# 69966
日期 01/15/2018
状态 Active
Type 综合文章
Tools
IP
的页面