2. 技术支持
  3. AR# 7019:
  4. AR# 70196: LogiCORE IP MIPI D-PHY v4.0 - On 7 Series Devices, High-Speed Lanes are unconnected in the synthesized design with Auto Calibration Auto and external IDELAYCTRL

AR# 70196

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LogiCORE IP MIPI D-PHY v4.0 - On 7 Series Devices, High-Speed Lanes are unconnected in the synthesized design with Auto Calibration Auto and external IDELAYCTRL

描述

On 7 Series devices, when using the MIPI D-PHY RX IP (Including the MIPI CSI-2 RX Subsystem) with Auto Calibration and external IDELAYCTRL, I can see in the synthesized design that the HS lanes are unconnected after the ISERDES.

How can I resolve this issue?

解决方案

This is a known issue for MIPI D-PHY IP and MIPI CSI-2 RX Subsystems, which only affects 7 Series devices:

  • Vivado 2017.3 - Users can download the MIPI D-PHY IP and MIPI CSI-2 RX Subsystem patch from (Xilinx Answer 70195) to work around this issue.
  • Vivado 2017.4 - This issue is resolved in the MIPI D-PHY LogiCORE IP in Vivado 2017.4 and later.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54550 LogiCORE IP MIPI D-PHY - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions N/A N/A
65242 MIPI CSI-2 Receiver Subsystem - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions N/A N/A
70195 2017.3 LogiCORE IP MIPI D-PHY v4.0 - Patch Updates for the MIPI D-PHY v4.0 N/A N/A
AR# 70196
日期 03/21/2018
状态 Active
Type 综合文章
器件
Tools
IP
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