How do I get a stable PHY link while using Xilinx evaluations boards that have a TIDP83867 PHY link in RGMII or SGMII mode?
Many of our evaluation boards use the TIDP83867 PHY link for Ethernet communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s.
On boards with this configuration, RX_CTRL has a pull down of 1K and so is set to Strap Mode 1.
RX D0 is set to Mode 1 with Pulldown of 1K, RX D2 is set to Mode 4 with pullup to 1K resulting in PHY Addr 5b01100.
But per the documentation linked to below, modes 1 and 2 are not applicable to RX_CTRL and it should be configured to strap MODE 3 or 4 only.
This applies to both the RGMII and SGMII PHY versions and can be found in the datasheets linked below:
If RX_CTRL is not strapped to mode 3 or 4, a software work-around sequence is needed: