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AR# 70919

Virtex UltraScale+ HBM Controller - Timing Violations on ARESET_N path

描述

Version Found: HBM v1.0

Version Resolved: See (Xilinx Answer 69267)

Timing can fail on the AXI reset path where the reset is generated synchronously from the HBM AXI Clock.

解决方案

Timing Violations on ARESET_N can be worked around by adding false paths as a work-around. 

A sample path/Tcl command is provided below:

set_false_path -through [get_pins {hmss_0/inst/hbm_inst/inst/*_STACK.u_hbm_top/AXI_*_ARESET_N}
 

Revision History:

04/10/2018New Answer Record in 2018.1

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69267 Virtex UltraScale+ HBM Controller - Release Notes and Known Issues N/A N/A
AR# 70919
日期 05/08/2018
状态 Active
Type 已知问题
器件
Tools
IP
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