This is the Master Answer Record for the ZCU111 RF Data Converter Evaluation Tool.
It lists known issues and limitations.
Each tile generates a fabric output clock which is used as the AXI stream clock to capture/stream the data in/out of each ADC/DAC slice. In other words, all slices within a tile have a common AXI stream clock.
As a result and to respect the ADC/DAC internal FIFO rates, the Interpolation/Decimation rate must be the same across a given tile.
2) Sample size
In BRAM mode, the current design supports sample size up to 64k samples in real mode, 32k samples in I/Q modes.
If these rules are violated, the design will return an error for the DAC but not for the ADC.
In DDR mode, the limit is depending on the host computer. A typical configuration should give access to 64M samples in total. For example, 1 DAC channel at 32M and 1 ADC channel at 32 M sample.
Sample size must be aligned to a multiple of 16 samples.
The FFT calculation is limited to 1M samples in the waveform window. The full data set can be imported/exported as per the limit above.
3) Windows path length issue
When running Vivado on a Windows platform, the user can encounter a project path length issue.
The error is most common when generating IP source files or when archiving a project.
Please refer to (Xilinx Answer 52787) for handling this issue.
Switching from Internal PLL enabled to bypass procedure (DAC):
Reprogram the external PLL with the desired sampling frequency.
When changing the sampling Frequency, the mixer settings are changed automatically. This is expected behavior.
It is recommended to refresh the tile and/or set the mixer frequency according to your requirements.
DAC Quad Band:
DAC Quad Band is selectable in the GUI. The GUI will then display the dual band configuration. The display is incorrect and quad band is indeed functional in the design.
This will be fixed in the 2018.3 release.
Error 5099: In MTS mode, on pressing Synchronization, the UI might generate Error 5099 (this occurs in 10% of cases).
The user needs to restart the board and re-run the test to validate MTS.
MTS: Only a sample clock frequency of value 3932.16MHz is supported for ADC and DAC.
MIxer settings: When the user is setting both mixer frequency and Nyquist zone, the mixer frequency can get altered.
You might need to re-correct the mixer frequency after setting the Nyquist zone.
Timing: The design is not completing timing cleanly, with approximate negative slack of 0.062ns. It will be fixed in the next release.