AR# 71778

UltraScale/UltraScale+ DDR4/DDR3 IP - Unable to Enter Self-Refresh when User Refresh is Enabled


Version Found: DDR4 v2.2 (Rev. 5)

Version Resolved: See (Xilinx Answer 69035)

When the Enable User Refresh and ZQCS Input option is enabled in the IP, and the Self-Refresh feature is also enabled, the DDR3/DDR4 core will not be able to enter the Self-Refresh state.

When this condition occurs, the user can assert app_sref_req but the core will never respond with the app_sref_ack assertion.


This happens because the self-refresh entry sequence inside the core is controlled by the refresh scheduler, and when user refresh is enabled, the refresh scheduler is not running because this is handled by user logic.

Because the refresh scheduler is not running, the DDR3/DDR4 interface will never enter the self-refresh state.

Currently there is no work-around for this behavior and the issue needs to be fixed with a tactical patch.

Please see the attached patches for Vivado 2018.1, 2018.2, and 2018.3.

This issue is scheduled to be fixed in the 2019.1 release of Vivado.

Note: the patch file names reference AR71852 but they apply to this Answer Record.

Revision History:

01/23/2019 - Initial Release




Answer Number 问答标题 问题版本 已解决问题的版本
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 71778
日期 04/16/2019
状态 Active
Type 已知问题
器件 More Less