AR# 71825


Zynq UltraScale+ MPSoC SD / eMMC clock has falling edge skew at 200 MHz (SDR104)


When SD / eMMC is running at 200 MHz (SDR104) the falling clock edge shows quantized jitter.


In SDR104 mode the DLL is driving the SD / eMMC clock. Per table 26-4 in (UG1085) the DLL is driven by the IOPLL or RPLL at 1500 MHz and the actual DLL divisor is 7.5. 

The resulting SD / eMMC device clock will be 200 MHz on the rising edge. To generate the 200 MHz  takes 15 IOPLL clock edges.

To maintain this odd number, the DLL will alternate between 7 and 8 IOPLL clocks from the rising edge to falling edge.

This is within the SD Clock Duty Cycle specification requirement of 30 - 70% for SDR104 as described in the Physical Layer Specification version 3.01.

AR# 71825
日期 12/20/2018
状态 Active
Type 综合文章
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