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AR# 7221

14.x Known Issue, Timing - For a design with two clocks/period constraints in the BUFGMUX, which constraint has priority in the final analysis?


My design has two clocks in the BUFGMUX in Virtex-II, Virtex-II Pro, Virtex-4, or Virtex-5 devices, with a period constraint on both.

Which one will have priority in the final analysis?


The period constraint that has the highest priority value (which is given through use of the PRIORITY keyword) is analyzed. 

The PRIORITY keyword is placed at the end of the TIMESPEC and is given a value. 

The lower the value, the higher the priority. 

If this fails, the constraint that appears last in the PCF file is analyzed in the final timing report.  

The input PERIOD constraints must be related for the PRIORITY keyword to impact the analysis correctly.

You can also place a PERIOD constraint on the output of a particular BUFGMUX clock net.

For more information, see (Xilinx Answer 9296)

AR# 7221
日期 07/08/2014
状态 Active
Type 综合文章
  • ISE Design Suite - 12
  • ISE Design Suite - 13
  • ISE Design Suite - 14