AR# 72322

描述

In a design using the DisplayPort in 4 Bytes mode, if I check the frequency of the RXOUTCLK/TXOUTCLK for the DisplayPort lanes (for example using Reports > Timing > Report Clock Networks as show in the below screen capture) I can see that the frequency is incorrectly set to 40.5MHz.

As per tables 3-1/3-2 of (PG230) it should be 135MHz (link clock at 5.4Gbps).

 

What is the reason for this issue and how can I resolve it?

解决方案

Root Cause:

In Vivado 2018.3, the tool is not processing the constraints files in the LogiCORE Video PHY Controller as expected. 

For this reason, the correct constraints are not applied.

• Note 1: This issue is happening in both 2 Bytes and 4 Bytes configurations
• Note 2: This issue has been identified in Vivado 2018.3 only and should not be happening for previous version of the tool
• Note 3: This issue has been identified only on 7 Series devices
  

Work-around:

To work around the issue, you can add the following constraints in your project XDC file:

2 Bytes configuration:

create_clock -period 3.703 [get_pins -of [get_cells -hierarchical -filter {name=~*gt*_dp_ss_vid_phy_controller_0_0_gtwrapper_i*gtxe2_i*}] -filter {REF_PIN_NAME == TXOUTCLK}]
create_clock -period 3.703 [get_pins -of [get_cells -hierarchical -filter {name=~*gt*_dp_ss_vid_phy_controller_0_0_gtwrapper_i*gtxe2_i*}] -filter {REF_PIN_NAME == RXOUTCLK}]

4 Bytes configuration:

create_clock -period 7.407 [get_pins -of [get_cells -hierarchical -filter {name=~*gt*_dp_ss_vid_phy_controller_0_0_gtwrapper_i*gtxe2_i*}] -filter {REF_PIN_NAME == TXOUTCLK}]
create_clock -period 7.407 [get_pins -of [get_cells -hierarchical -filter {name=~*gt*_dp_ss_vid_phy_controller_0_0_gtwrapper_i*gtxe2_i*}] -filter {REF_PIN_NAME == RXOUTCLK}]

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