In my DisplayPort RX (sink) application, when plugging and unplugging the IP many times or powering and powering off the chip many times, I can see that the CPLL becomes unresponsive.
Looking at my system output, it reports that the link is up, but there is no video out of the core.
This problem can be fixed by replugging or power-cycling the board.
What is the issue and how can I fix it?
(Xilinx Answer 69421) states that the CPLL is required to be put into a power-down state when there is no active clock.
In several cases when using specific power supplies it is possible to enter into a state where the drivers do not put the CPLL into the power-down state using the updates from the Answer Record.
This has been seen in a very limited number of cases.
If you believe you are running into this issue after many plug/unplug or power events, please upgrade to 2019.1 or see the Answer Record below for a patch in 2018.3.