When I run compile_simlib with the target simulator set to IES, the following error is seen for the IP Zynq UltraScale+ sync_ip_v1_0.
ncvlog: *E,ERRIPR: error within protected source code.
The issue will be fixed in the 2019.2 release.
If your design does not utilize this IP, you can ignore the failure.
If you need a fix for the 2019.1 version, please contact Xilinx Technical Support.