AR# 72795

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2019.1 compile_simlib - Zynq UltraScale+ sync_ip_v1_0 fails to compile with IES

描述

When I run compile_simlib with the target simulator set to IES, the following error is seen for the IP Zynq UltraScale+ sync_ip_v1_0.

ncvlog: *E,ERRIPR: error within protected source code.

解决方案

The issue will be fixed in the 2019.2 release.

If your design does not utilize this IP, you can ignore the failure.

If you need a fix for the 2019.1 version, please contact Xilinx Technical Support.

AR# 72795
日期 10/25/2019
状态 Active
Type 已知问题
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