AR# 73051

2019.1/2019.2 Zynq UltraScale+ MPSoC VCU - Why do I see a high decoder latency number while decoding a reduced latency HEVC encoded stream?

描述

Why do I see a high decoder latency number while decoding a reduced latency HEVC encoded stream?

Example Pipeline:

  1. Boot up the latest 2019.2 VCU TRD images.

  2. GST_DEBUG="*omx*:8" GST_DEBUG_FILE=trace.log gst-launch-1.0 -v v4l2src io-mode=4 device=/dev/video0 ! video/x-raw, width=1920, height=1080, format=NV12, framerate=60/1 ! omxh265enc control-rate=low-latency target-bitrate=20000 filler-data=0 prefetch-buffer=TRUE ! video/x-h265, alignment=au ! queue max-size-buffers=0 ! omxh265dec low-latency=1 ! queue max-size-bytes=0 ! fpsdisplaysink name=fpssink text-overlay=false 'video-sink=kmssink bus-id=a0070000.v_mix plane-id=30 hold-extra-sample=1 show-preroll=false sync=true' sync=true -v

  3. cat trace.log | grep latency

解决方案

This is a known issue with the Zynq UltraScale+ MPSoC - LogiCORE H.264/H.265 Video Codec Unit (VCU) that occurs when decoding a reduced latency encoded bitstream in HEVC mode.

This issue was introduced due to a change in Decoded Picture Buffer (DPB) mode.

  • 2019.1 - Users can download the PetaLinux Recipes and Patch files from (Xilinx Answer 72324) to work around this issue
  • 2019.2 - Users can download the PetaLinux Recipes and Patch files from (Xilinx Answer 73019) to work around this issue
  • 2020.1 - This issue will be resolved in the 2020.1 release and later versions

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AR# 73051
日期 12/19/2019
状态 Active
Type 已知问题
Tools
IP