When reading the MSA values from the DisplayPort RX Subsystem IP I can see that the values are not the expected values.
It does not seem to be related to the issue in (Xilinx Answer 70130) because the MSA values do not make sense and are changing when I change the resolution from the source.
What could be the reason for the incorrect MSA values?
The MSA values are sent by the source through the data stream (once per frame during blanking periods).
The first thing to check is to make sure that the source is sending the correct values.
Checking with multiple sinks can help to confirm this.
Also, it is important to note that the GPU might pretend to send a video resolution when it is only scaling the content of the video. See (Xilinx Answer 70130) for more information.
If you have identified that the issue is coming from the Xilinx DisplayPort RX Subsystem IP, this could be a symptom of having the DisplayPort data lanes swapped.
To confirm this, check that the data lanes are correctly mapped.
Note that the Xilinx Video PHY is expecting the GT lanes to be aligned (i.e. DP lane 0 assigned to GT lane 0, DP lane 1 assigned to GT lane 1...) and is generating XDC constraints accordingly.
These constraints could potentially overwrite the user's constraints. Checking the implemented checkpoint (DCP) is the best way to confirm the location of the DisplayPort lanes.