AR# 73714

UltraScale/UltraScale+ Memory IP - Locked IPs from Earlier Versions of Vivado when Brought in to 2020.1 or Later Will Encounter Errors During Implementation or in Hardware


  • DDR4 v2.2 (Rev. 9)
  • DDR3 v1.4 (Rev. 9)
  • RLDRAM3 v1.4 (Rev. 9)
  • QDRII+ v1.4 (Rev. 9)
  • QDRIV v2.0 (Rev. 9)
  • LPDDR3 v1.0 (Rev. 9)

解决问题的版本: 查看 (Xilinx 答复 58435)


To prevent errors during implementation or while running in hardware, the following parameter must be added to the design before running synthesis:

set_param project.replaceDontTouchWithKeepHierarchySoft 1

This behavior only applies to designs generated prior to 2020.1, and then brought in to 2020.1 or later, while also keeping the IP locked without upgrading to the current version of Vivado.

If the IP is generated in Vivado 2020.1 or later, or if the IP was from an earlier version and then brought in to 2020.1 or later and upgraded, then this parameter does not need to be set and no additional actions are required.


06/03/2020 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
58435 MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions N/A N/A


AR# 73714
日期 06/04/2020
状态 活跃
Type 已知问题
器件 More Less
IP More Less