We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 9150

5.1i CPLD CPLDFit/Hitop - Error: "Insufficient number of input pins (error:hi300, hi301)"


General Description:

When I fit a design, an error message similar to the following appears:

"Insufficient number of input pins:

Needs at least 27 but only 12 left after allocating other resources.

Device XC9572XL-PC44 was disqualified.

ERROR:hi300 - The design requires too many resources to fit in any of the specified devices. You may want to decrease the pterm limit for a denser fit, or split the design into sub- designs, or try a larger device."


This occurs simply because more I/O is present in your design than is available in the particular device/package combination. The possible resolutions to this are:

1. Change your design to reduce the I/O count.

2. See if this particular device has a larger package with more I/O. For example, an XC9536XL-PC44 has 34 I/O, but an XC9536XL-VQ64 has 36 I/O. (This can be seen on Table 2 of the XC9500/XL data sheet at: http://www.xilinx.com/partinfo/databook.htm#cpld.)

3. If the device is a CoolRunner XPLA3, the JTAG pins may be used as I/O. This is the only Xilinx CPLD that has this feature. You may gain four I/O pins by not dedicating the JTAG pins for ISP functionality. For more information on doing this, please see (Xilinx Answer 8455).

4. Use a larger device in the family that contains more I/O pins.

AR# 9150
日期 12/15/2012
状态 Active
Type 综合文章