When my Verilog design is loaded in ModelSim, the UniSim libraries are not used, even though I have them mapped correctly. Why does this happen?
The library mapping information displays logical library names to physical locations. These mappings are not used as a search list when simulation is loaded in ModelSim.
For Verilog, a library search list needs to be specified. This can be done either through a `uselib directive in the source code, or while the simulation is loading in ModelSim. The VSim command line would look like:
vsim -L <library_name> work.toplevel work.glbl
where <library_name> will be the UniSim/SimPrim library to be used.
The syntax for the 'uselib command is as follows:
where the <library_mapping_name> is the alias assigned to the library in ModelSim. To see what these libraries have been mapped to, go to Design -> Browse Libraries from the pull-down menu in ModelSim.
If this switch is not used, errors similar to the following occur:
"# ERROR: C:/pathtofile/myfilename.v(96): Instantiation of 'SRL16' failed (design unit not found).
# Region: /myfilename
# Searched libraries:
For more information on the usage of the "glbl.v" file, please see (Xilinx Answer 6537).