Spartan 7 SP701 FPGA Evaluation Kit
发布者: AMD
The SP701 Evaluation Kit, equipped with the best-in-class performance-per-watt Spartan 7 FPGA, is built for designs requiring sensor fusion such as industrial networking, embedded vision, and automotive applications.
Overview
Product Description
The SP701 Evaluation Kit, equipped with the best-in-class performance-per-watt Spartan™ 7 FPGA, is built for designs requiring sensor fusion such as industrial networking, embedded vision, and automotive applications. The SP701 features high I/O availability and I/O expansion capability via Pmods and FMC connectors, making it the largest IP development canvas for Spartan 7 FPGA users. The included XC7S100 FPGA is the highest density device of the Spartan 7 family. With 102K logic cells and 400 I/O pins, the XC7S100 pairs expandable connectivity with high processing capability, all in a form factor ideal for edge applications.
Connectivity for sensor heavy applications
- Video interfaces including MIPI CSI, DSI, and HDMI
- Expandable I/O via Pmods and FPGA Mezzanine Card (FMC) interfaces
- Dual ethernet for industrial networking
Best-in-class performance and flexibility with the largest Spartan 7 device
- Built for connectivity with 400 available I/O pins
- Scalable across the industry’s broadest cost-optimized portfolio
Key Features & Benefits
Easy-to-use soft processor options for embedded applications
- Pre-configured MicroBlaze™ application processor, real-time processor, and microcontroller Example Designs with up to 200DMIPS of processing power
- Arm® Cortex®-M1 and Cortex-M3 DesignStart FPGA available
Free Vivado™ HL WebPACK™ Edition support
- Includes AMD Software Development Kit (XSDK) for C compilation and debug
- Customize designs quickly and easily with drag & drop peripherals
Featured AMD Devices
Featuring the Spartan 7 XC7S100 FPGA
| System Logic Cells | 102,400 |
|---|---|
| Memory | 1,100Kb DRAM, 4,320Kb Block RAM |
| DSP Slices | 160 |
| Maximum I/O Pins | 400 |
| Additional Features | 8 clock management tiles (1MMCM + 1 PLL) |
| 1 analog to digital converter (XADC) | |
| 1 configuration AES / HMC Block |
Product Information
Board Features
Featuring the Spartan™ 7 XC7S100 FPGA
| Board Specifications | Value |
|---|---|
| Length | 6 inch (152.4 mm) |
| Height | 6 inch (152.4 mm) |
| Thickness (+/-5%) | 0.088 inch (2.24 mm) |
| Operating Environmental Temperature | 0◦C to +45◦C |
| Storage Environmental Temperature | -25◦C to +60◦C |
| Configuration | |
| JTAG | Yes |
| SPI | Yes |
| QSPI | Yes |
| Memory | |
| DDR3L | 4Gb (256M x 16) |
| Quad-SPI Flash | 1Gb |
| I2C EEPROM | 32Kb |
| Control & I/O | |
| User pushbuttons | 5 |
| DIP switches | 16 |
| User LEDs | 8 |
| System Controller | Yes |
| PMBUS | Yes |
| Expansion Connectors | |
| VITA 57.1 FMC LPC | 1 |
| Pmod Headers | 6 |
| Communication & Networking | |
| UART to USB Bridge | 1 |
| RJ-45 Tri-Speed Ethernet Connectors | 2 |
| Display | |
| HDMI Video Output | Yes |
| MIPI-CSI Camera Interface | Yes |
| MIPI-DSI Display Interface | Yes |
| Clocking | |
| I2C Programmable Clock | Yes |
| Power | |
| 12V Wall Adapter | Yes |
What's Inside the Box
Featuring the Spartan™ 7 XC7S100 FPGA
Resources
标题
日期
Design Tools
| Name | Description | License Type |
|---|---|---|
| Vivado™ Design Suite: System Edition | The AMD Vivado Design Suite is a revolutionary IP and system centric design environment built from the ground up to accelerate the design for all programmable devices. | Node-locked and device-locked to the XC7S100 FPGA, with one year of updates |
| AMD SDK | Full suite of tools for embedded software development and debug targeting AMD platforms. | Included |
| PetaLinux Tools | Configure, build, and deploy Linux operating system to AMD platforms. | Included |
Intellectual Property
| Name | Description | License Type |
|---|---|---|
| MIPI | MIPI CSI (RX/TX) and MIPI DSI (TX) | Node-locked and device-locked to the XC7S100 FPGA, with one year of updates |
| Ethernet MAC (TEMAC) | 10/100/1000Mb/s Tri-mode Ethernet MAC IP | Node-locked and device-locked to the XC7S100 FPGA, with one year of updates |
| Memory Interface Generator (MIG) | MIG is a free software tool used to generate memory controllers and interfaces for AMD FPGAs. | Included |
Additional Tools, IP and Resources
| Provider Name | Product Category | Item | Description |
|---|---|---|---|
| Open Source | Software Tool | TeraTerm | One of many possible terminal emulators used for serial connection from your PC to the evaluation kit. |
