QOID: QOI Lossless Image Compression Decoder

  • 产品编号: QOID
  • 供应商: CAST, Inc.
  • Partner Tier: Elite Certified

产品描述

The QOID Core is a decoder that implements a highly efficient, low-power, lossless image decompression engine compliant with the Quite OK Image format (QOI) specification, version 1.0. The QOI algorithm compresses RGB or RGBA images with 8 bits per color without any loss. It has a compression efficiency close to that of the PNG compression, at a fraction of the computational complexity. Capitalizing on the simplicity of the QOI algorithm, the QOID decoder core can decompress images at a very high speed and with minimal silicon resources. The core occupies approximately 200 LUTs and can decode one pixel per clock cycle. A single core instance can decompress images at rates sufficient for UHD 4k60 on Kintex® UltraScaleTM or Kintex® UltraScale+TM. The core is designed for ease of use and integration and adheres to coding and verification best practices. It requires no assistance from a host processor and uses simple handshake interfaces for input and output data. Technology mapping, timing closure, and scan insertion are trouble-free, as the core contains no multi-cycle or false paths and uses only rising-edge-triggered D-type flip-flops, no tri-states, and a single-clock/reset domain. Its reliability and low risk have been proven through rigorous verification and FPGA validation.


主要特性与优势

  • Available in VHDL or Verilog RTL source code or targeted FPGA netlist
  • Supports 24-bit RGB and optionally 32-bit RGBA
  • UHD/4k capable with just 200L UTs
  • Lossless Image Decompression per QOI Image Format

特色技术文档

器件实现矩阵

面向此核实现范例的器件使用矩阵。联系供应商了解更多信息。

系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Kintex-UP Family XCKU11P -3 Vivado 2020.2 0 199 0 0 0 0 750
KINTEX-U Family XCKU085 -3 Vivado 2020.2 0 197 0 0 0 0 500

IP 质量指标

综合信息

数据创建日期 Jun 03, 2022
当前 IP 修订号 1v00
当前修订日期已发布 May 12, 2022
第一版发布日期 May 12, 2022

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 0
可否提供参考? N

交付内容

可供购买的 IP 格式 Source Code, Netlist
源代码格式 VHDL, Verilog
是否包含高级模型? Y
模型格式 C
提供集成测试台 Y
集成测试台格式 Verilog, VHDL
是否提供代码覆盖率报告? N
是否提供功能覆盖率报告? N
是否提供 UCF? XDC
商业评估板是否可用? N
评估板所用的 FPGA N/A
是否提供软件驱动程序? N/A
驱动程序的操作系统支持 OS Independent

实现方案

代码是否针对 Xilinx 进行优化? N
定制 FPGA 优化技术 None
所支持的综合软件工具及版本 Xilinx XST; Synplicity Synplify; Mentor Precision; Vivado Synthesis
是否执行静态时序分析? N
是否包含 IP-XACT 元数据? N

验证

是否有可用的文档验证计划? Yes, document only plan
测试方法 Directed Testing
断言 N
收集的覆盖指标 Code
是否执行时序验证? Y
可用的时序验证报告 Y
所支持的仿真器 Cadence NC-Sim; Cadence IUS; Mentor ModelSIM; Mentor Questa; Synopsys VCS

硬件验证

在 FPGA 上进行验证 N
已通过的行业标准合规测试 N/A
是否提供测试结果? N