logi3D Scalable 3D Graphic Accelerator

  • 产品编号: logi3D
  • 供应商: Xylon d.o.o.
  • Partner Tier: Premier


The logi3D IP core is specifically designed for the AMD Versal Adaptive Compute Acceleration Platform (ACAP) and AMD Zynq 7000 SoC family. SoC designers can add attractive 3D graphics, including advanced Graphical User Interfaces (GUI), to their AMD ACAP/SoC design by combining the logi3D with their application specific IP cores in a plug-and-play manner. The IP core is designed to support the OpenGL ES 1.1. API. Currently supported operating system is Linux. Due to its AMBA AXI4 interface compliance the logi3D IP core can also be implemented on AMD 7 Series and other AMD FPGA families as a Graphics Processing Unit (GPU) in various ASSP plus FPGA combinations.

The logi3D IP core has a small footprint and enables efficient implementation in the smallest Versal ACAP device. It enables system designers to fully exploit heterogeneous computing and networking resources available on the unique AMD Adaptive Compute Acceleration Platform, and to round their design with graphics capability.

* Product is based on published Khronos Specification, and is expected to pass the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.


  • The logi3D GPU can be used with different CPUs
  • ARM processing system (1 core) runs the geometry engine and optimizes the IP's size
  • Programmable logic resource-effective 3D graphics acceleration
  • Linux OS compatible
  • Conformant to the AMBA AXI4 bus specifications from ARM
  • Graphics accelerator IP designed to support the OpenGL ES 1.1 API (Common Profile)
  • Supports Safety Critical OpenGL SC 1.0.1




系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VERSAL_AI_CORE Family XCVC1902 -1 Vivado 2020.2 Y 0 49143 46 21 0 0 180
Zynq-7000 Family XC7Z020 -1 Vivado 2018.3 Y 7706 25540 14 38 0 0 170

IP 质量指标


数据创建日期 Jul 21, 2023
当前 IP 修订号 3.0
当前修订日期已发布 Feb 26, 2021
第一版发布日期 Jan 01, 2007

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 15
可否提供参考? N


可供购买的 IP 格式 Netlist, Source Code, Bitstream
源代码格式 VHDL
是否包含高级模型? Y
模型格式 C++
提供集成测试台 Y
集成测试台格式 VHDL
是否提供代码覆盖率报告? N
是否提供功能覆盖率报告? N
是否提供 UCF? UCF
商业评估板是否可用? Y
评估板所用的 FPGA Spartan-6
是否提供软件驱动程序? Y
驱动程序的操作系统支持 Linux, WEC, Android


代码是否针对 Xilinx 进行优化? Y
标准 FPGA 优化技术 Inference, Instantiation
定制 FPGA 优化技术 The IP targeted to Xilinx EPP and FPGA.
所支持的综合软件工具及版本 Xilinx XST / 13.2
是否执行静态时序分析? Y
AXI 接口 AXI4-Lite, AXI4
是否包含 IP-XACT 元数据? N


是否有可用的文档验证计划? No
测试方法 Directed Testing
断言 Y
收集的覆盖指标 None
是否执行时序验证? Y
可用的时序验证报告 Y
所支持的仿真器 Mentor ModelSIM / 6.4c


在 FPGA 上进行验证 Y
所使用的硬件验证平台 VCK190, ZC706, ZedBoard
已通过的行业标准合规测试 N
是否提供测试结果? N