ZipAccel-C is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards.
The core receives uncompressed input files and produces compressed files. No post processing of the compressed files is required, as the core encapsulates the com-pressed data payload with the proper headers and footers. Input files can be segmented, and segments from different files can be interleaved at the core’s input.
The core’s flexible architecture enables fine-tuning of its compression efficiency, throughput, and latency to match the requirements of the end application. Throughputs in excess of 100 Gbps are feasible even in low-cost FPGAs, and latency can be as small as 13 clock cycles.
ZipAccel-C offers compression efficiency practically equivalent to today’s popular deflate-based software applications. Analyzing processing speed versus compression efficiency to achieve the best trade off for a specific system is facilitated by the included software model, and by support from our team of data compression experts.
- Flexible architecture allows fine-tuning Throughput, Compression Efficiency, and Latency to match application requirements.
- Compression efficiency can be on par with Unix/Linux max compression option (gzip -9)
- Latency from 13 clock cycles (Static Huffman)
- FPGA resources requirements from 15k LUTs
- Supports Deflate (RFC-1951), ZLIB (RFC-1950) & GZIP (RFC-1952).
- More than 100Gbps with one core instance, scalable to meet any throughput requirement