GZIP/ZLIB/Deflate Data Compression Core

  • 产品编号: Zipaccel-C
  • 供应商: CAST, Inc.
  • Certified Partner


ZipAccel-C is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards. The core receives uncompressed input files and produces compressed files. No post processing of the compressed files is required, as the core encapsulates the com-pressed data payload with the proper headers and footers. Input files can be segmented, and segments from different files can be interleaved at the core’s input. The core’s flexible architecture enables fine-tuning of its compression efficiency, throughput, and latency to match the requirements of the end application. Throughputs in excess of 100 Gbps are feasible even in low-cost FPGAs, and latency can be as small as 13 clock cycles. ZipAccel-C offers compression efficiency practically equivalent to today’s popular deflate-based software applications. Analyzing processing speed versus compression efficiency to achieve the best trade off for a specific system is facilitated by the included software model, and by support from our team of data compression experts.


  • Flexible architecture allows fine-tuning Throughput, Compression Efficiency, and Latency to match application requirements.
  • Compression efficiency can be on par with Unix/Linux max compression option (gzip -9)
  • Latency from 13 clock cycles (Static Huffman)
  • FPGA resources requirements from 15k LUTs
  • Supports Deflate (RFC-1951), ZLIB (RFC-1950) & GZIP (RFC-1952).
  • More than 100Gbps with one core instance, scalable to meet any throughput requirement



系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-U Family XCKU085 -1 Vivado ML 2022.1 Y 0 4021 2 0 0 0 350
Kintex-UP Family XCKU9P -1 Vivado ML 2022.1 Y 0 3980 2 0 0 0 450
VERSAL_PREMIUM Family XCVP1202 -2 Vivado ML 2022.1 900 4058 1 0 0 0 450
Artix-UP Family XCAU25P -1 Vivado ML 2022.1 0 4019 2 0 0 0 500
KINTEX-7 Family XC7K325T -1 Vivado 2018.2 Y 2679 7012 5 0 0 0 200

IP 质量指标


数据创建日期 Nov 28, 2022
当前 IP 修订号 3.1c
当前修订日期已发布 May 12, 2022
第一版发布日期 Mar 09, 2012

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 12
可否提供参考? Y


可供购买的 IP 格式 Netlist, Source Code
源代码格式 Verilog
是否包含高级模型? N
模型格式 C
提供集成测试台 Y
集成测试台格式 Verilog
是否提供代码覆盖率报告? N
是否提供功能覆盖率报告? N
是否提供 UCF? UCF & SDF
商业评估板是否可用? Y
评估板所用的 FPGA Kintex UltraScale
是否提供软件驱动程序? Y
驱动程序的操作系统支持 Linux Fedora 20 or later


代码是否针对 Xilinx 进行优化? Y
标准 FPGA 优化技术 Inference
定制 FPGA 优化技术 None
所支持的综合软件工具及版本 Vivado Synthesis; Xilinx XST
是否执行静态时序分析? Y
AXI 接口 AXI4-Stream
是否包含 IP-XACT 元数据? Y


是否有可用的文档验证计划? No
测试方法 Both
断言 N
收集的覆盖指标 Code
是否执行时序验证? Y
可用的时序验证报告 Y
所支持的仿真器 Mentor ModelSIM; Mentor Questa; Cadence NC-Sim


在 FPGA 上进行验证 Y
所使用的硬件验证平台 KCU105
已通过的行业标准合规测试 N/A
是否提供测试结果? N