CAN 2.0, CAN FD, & CAN-XL Controller

  • 产品编号: CAN-CTRL
  • 供应商: CAST, Inc.
  • Partner Tier: Elite Certified

产品描述

Implements a CAN bus controller that performs serial communication according to the CAN 2.0, CAN FD, and CAN XL specifications. The CAN-CTRL core is easy to use and integrate, featuring programmable interrupts, data and baud rates; a configurable number of independently programmable acceptance filters; and a generic processor interface or optionally an AMBA APB, or AHB-Lite interface. The number of receive buffers is synthesis-time configurable. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). The PTB can store one message, while the number of included buffer slots for the STB is synthesis-time configurable. The transmit buffer can operate in FIFO or priority mode. The core implements functionality similar to the Philips SJA1000 working with its PeliCAN mode extensions, providing error analysis, diagnosis, system maintenance, and optimization features. The CAN-CTRL is available in two versions: Normal, and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The deliverables for this version include a Safety Manual (SAM), a Failure Modes, Effects and Diagnostics Analysis (FMEDA), and the ISO-26262 ASIL-B Ready certificate, issued by SGS-TÜV Saar GmbH. The core is extensively verified, proven in several plug fests and a large number of production designs.


主要特性与优势

  • Optional Safety Enhanced Version implements ECC for SRAM and spatial redundancy for inner logic protection, and it is ISO-26262 ASIL-D Ready.
  • Supports CAN 2.0 & CAN-FD (ISO 11898-1.2015), TTCAN (ISO 11898-4 level 1), and CAN XL (CiA 601-1)
  • Optimized for AUTOSAR and SAE J1939
  • Enhanced Functionality: Reports bus errors and supports Listen-Only and Loop-Back modes, enabling traffic analysis, bit-rate detection, and shelf-testing.
  • Configuration Options: Number of Rx & Tx buffers, number of acceptance filters, number of CAN nodes and host bus type (AHB-Lite, APB or generic uP).
  • Maturity: Multiple times production proven. Proven with different transceivers and tested in CAN-FD plug-fests

特色技术文档

器件实现矩阵

面向此核实现范例的器件使用矩阵。联系供应商了解更多信息。

系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Kintex-UP Family XCKU3P -3 Vivado 2018.3 N 298 1559 1 0 0 0 80
ARTIX-7 Family XC7A12T -3 Vivado 2018.3 Y 517 1531 1 0 0 0 80
KINTEX-U Family XCKU035 -2 Vivado 2018.3 Y 275 1560 1 0 0 0 80

IP 质量指标

综合信息

数据创建日期 Jul 12, 2022
当前 IP 修订号 7x10n00s00
当前修订日期已发布 Mar 17, 2020
第一版发布日期 Feb 18, 2000

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 120
可否提供参考? Y

交付内容

可供购买的 IP 格式 Netlist, Source Code
源代码格式 VHDL, Verilog
是否包含高级模型? N
提供集成测试台 Y
集成测试台格式 Verilog, VHDL
是否提供代码覆盖率报告? Y
是否提供功能覆盖率报告? Y
是否提供 UCF? UCF
商业评估板是否可用? N
是否提供软件驱动程序? N
驱动程序的操作系统支持 N/A

实现方案

代码是否针对 Xilinx 进行优化? Y
标准 FPGA 优化技术 Inference
定制 FPGA 优化技术 BRAMs
所支持的综合软件工具及版本 Mentor Precision; Synplicity Synplify; Xilinx XST
是否执行静态时序分析? N
AXI 接口 AXI4-Lite
是否包含 IP-XACT 元数据? N

验证

是否有可用的文档验证计划? Yes, document only plan
测试方法 Both
断言 N
收集的覆盖指标 Code
是否执行时序验证? Y
可用的时序验证报告 Y
所支持的仿真器 Mentor Questa; Mentor ModelSIM; Cadence NC-Sim

硬件验证

在 FPGA 上进行验证 Y
所使用的硬件验证平台 Kintex7
已通过的行业标准合规测试 N
特定的合规测试 N/A